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    <title>topic Re: IMX8ULP Integrate LPSPI with FreeRTOS ping-pong example in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX8ULP-Integrate-LPSPI-with-FreeRTOS-ping-pong-example/m-p/1758560#M215842</link>
    <description>&lt;P&gt;Adding that doesn't seem to help, It freezes after SRTM init:&lt;/P&gt;&lt;P&gt;LPSPI board to board edma example.&lt;BR /&gt;This example use one board as master and another as slave.&lt;BR /&gt;Master and slave uses EDMA way. Slave should start first.&lt;BR /&gt;Please make sure you make the correct line connection. Basically, the connection is:&lt;BR /&gt;LPSPI_master -- LPSPI_slave&lt;BR /&gt;CLK -- CLK&lt;BR /&gt;PCS -- PCS&lt;BR /&gt;SOUT -- SIN&lt;BR /&gt;SIN -- SOUT&lt;BR /&gt;GND -- GND&lt;BR /&gt;Start SRTM communication&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;This is in the LPSPI example:&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;if&lt;/SPAN&gt;&lt;SPAN&gt; (&lt;/SPAN&gt;&lt;SPAN&gt;BOARD_IsLowPowerBootType&lt;/SPAN&gt;&lt;SPAN&gt;() &lt;/SPAN&gt;&lt;SPAN&gt;!=&lt;/SPAN&gt; &lt;SPAN&gt;true&lt;/SPAN&gt;&lt;SPAN&gt;)&lt;/SPAN&gt;&lt;SPAN&gt; /* not low power boot type */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;BOARD_HandshakeWithUboot&lt;/SPAN&gt;&lt;SPAN&gt;();&lt;/SPAN&gt;&lt;SPAN&gt; /* Must handshake with uboot, unless will get issues(such as: SoC reset all the&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;time) */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; }&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;else&lt;/SPAN&gt;&lt;SPAN&gt; /* low power boot type */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;BOARD_SetTrdcGlobalConfig&lt;/SPAN&gt;&lt;SPAN&gt;();&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; }&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;I didn't include&amp;nbsp;BOARD_SetTrdcGlobalConfig() because this isn't a low power boot, I want to run the A35 and M33 cores together.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;</description>
    <pubDate>Thu, 16 Nov 2023 18:56:39 GMT</pubDate>
    <dc:creator>shaunakk</dc:creator>
    <dc:date>2023-11-16T18:56:39Z</dc:date>
    <item>
      <title>IMX8ULP Integrate LPSPI with FreeRTOS ping-pong example</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8ULP-Integrate-LPSPI-with-FreeRTOS-ping-pong-example/m-p/1756551#M215653</link>
      <description>&lt;P&gt;I am trying to integrate the lpspi_edma_b2b_transfer_master example with the rpmsg_lite_pingpong_rtos example. When I run the LPSPI EDMA standalone example I don't run into any problems, but when running it in the RPMSG example, the callback&amp;nbsp;&amp;nbsp;&lt;SPAN&gt;LPSPI_MasterUserCallback never fires.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I have tried setting the interrupt priorities:&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;NVIC_SetPriority&lt;/SPAN&gt;&lt;SPAN&gt;(LPSPI1_IRQn, &lt;/SPAN&gt;&lt;SPAN&gt;configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;NVIC_SetPriority&lt;/SPAN&gt;&lt;SPAN&gt;(DMA0_1_IRQn, &lt;/SPAN&gt;&lt;SPAN&gt;configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;NVIC_SetPriority&lt;/SPAN&gt;&lt;SPAN&gt;(DMA0_0_IRQn, &lt;/SPAN&gt;&lt;SPAN&gt;configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY&lt;/SPAN&gt;&lt;SPAN&gt;);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;I have a feeling the app SRTM is messing with the pins on header J23 (LPSPI1)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;I have also removed the line to sync with u-boot, as app_srtm seems to handle that. Attached is my project.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;Thanks!&lt;/SPAN&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Tue, 14 Nov 2023 00:52:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8ULP-Integrate-LPSPI-with-FreeRTOS-ping-pong-example/m-p/1756551#M215653</guid>
      <dc:creator>shaunakk</dc:creator>
      <dc:date>2023-11-14T00:52:21Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8ULP Integrate LPSPI with FreeRTOS ping-pong example</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8ULP-Integrate-LPSPI-with-FreeRTOS-ping-pong-example/m-p/1757268#M215730</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/225685"&gt;@shaunakk&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Please add more debug messages or provide your debug results for us to better analyze this case.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 15 Nov 2023 02:57:54 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8ULP-Integrate-LPSPI-with-FreeRTOS-ping-pong-example/m-p/1757268#M215730</guid>
      <dc:creator>Zhiming_Liu</dc:creator>
      <dc:date>2023-11-15T02:57:54Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8ULP Integrate LPSPI with FreeRTOS ping-pong example</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8ULP-Integrate-LPSPI-with-FreeRTOS-ping-pong-example/m-p/1757409#M215746</link>
      <description>&lt;P&gt;If you look at my code, it is just getting stuck on the line where it waits for isTransferCompleted to be true. I don’t have any other debug logs, all I know is the callback isn’t getting called and there is no data sent on LPSPI1&lt;/P&gt;</description>
      <pubDate>Wed, 15 Nov 2023 07:50:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8ULP-Integrate-LPSPI-with-FreeRTOS-ping-pong-example/m-p/1757409#M215746</guid>
      <dc:creator>shaunakk</dc:creator>
      <dc:date>2023-11-15T07:50:48Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8ULP Integrate LPSPI with FreeRTOS ping-pong example</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8ULP-Integrate-LPSPI-with-FreeRTOS-ping-pong-example/m-p/1758085#M215805</link>
      <description>&lt;P&gt;Check your source code and find that you didn't add&amp;nbsp;&lt;STRONG&gt;&lt;SPAN&gt;BOARD_SetTrdcGlobalConfig, &lt;/SPAN&gt;&lt;/STRONG&gt;&lt;SPAN&gt;please do more double-check after migrating these two examples.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 16 Nov 2023 05:57:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8ULP-Integrate-LPSPI-with-FreeRTOS-ping-pong-example/m-p/1758085#M215805</guid>
      <dc:creator>Zhiming_Liu</dc:creator>
      <dc:date>2023-11-16T05:57:29Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8ULP Integrate LPSPI with FreeRTOS ping-pong example</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8ULP-Integrate-LPSPI-with-FreeRTOS-ping-pong-example/m-p/1758560#M215842</link>
      <description>&lt;P&gt;Adding that doesn't seem to help, It freezes after SRTM init:&lt;/P&gt;&lt;P&gt;LPSPI board to board edma example.&lt;BR /&gt;This example use one board as master and another as slave.&lt;BR /&gt;Master and slave uses EDMA way. Slave should start first.&lt;BR /&gt;Please make sure you make the correct line connection. Basically, the connection is:&lt;BR /&gt;LPSPI_master -- LPSPI_slave&lt;BR /&gt;CLK -- CLK&lt;BR /&gt;PCS -- PCS&lt;BR /&gt;SOUT -- SIN&lt;BR /&gt;SIN -- SOUT&lt;BR /&gt;GND -- GND&lt;BR /&gt;Start SRTM communication&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;This is in the LPSPI example:&lt;/P&gt;&lt;DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;if&lt;/SPAN&gt;&lt;SPAN&gt; (&lt;/SPAN&gt;&lt;SPAN&gt;BOARD_IsLowPowerBootType&lt;/SPAN&gt;&lt;SPAN&gt;() &lt;/SPAN&gt;&lt;SPAN&gt;!=&lt;/SPAN&gt; &lt;SPAN&gt;true&lt;/SPAN&gt;&lt;SPAN&gt;)&lt;/SPAN&gt;&lt;SPAN&gt; /* not low power boot type */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;BOARD_HandshakeWithUboot&lt;/SPAN&gt;&lt;SPAN&gt;();&lt;/SPAN&gt;&lt;SPAN&gt; /* Must handshake with uboot, unless will get issues(such as: SoC reset all the&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;time) */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; }&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;else&lt;/SPAN&gt;&lt;SPAN&gt; /* low power boot type */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &lt;/SPAN&gt;&lt;SPAN&gt;BOARD_SetTrdcGlobalConfig&lt;/SPAN&gt;&lt;SPAN&gt;();&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; }&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;I didn't include&amp;nbsp;BOARD_SetTrdcGlobalConfig() because this isn't a low power boot, I want to run the A35 and M33 cores together.&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Thu, 16 Nov 2023 18:56:39 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8ULP-Integrate-LPSPI-with-FreeRTOS-ping-pong-example/m-p/1758560#M215842</guid>
      <dc:creator>shaunakk</dc:creator>
      <dc:date>2023-11-16T18:56:39Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8ULP Integrate LPSPI with FreeRTOS ping-pong example</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8ULP-Integrate-LPSPI-with-FreeRTOS-ping-pong-example/m-p/1759470#M215927</link>
      <description>&lt;P&gt;The RDC is resource manager between M core and A core, so we should config it. For no low power boot, you can refer&amp;nbsp; the&amp;nbsp;&lt;SPAN&gt;BOARD_HandshakeWithUboot function. It also configure the RDC.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Zhiming_Liu_0-1700447357309.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/250560iD2E6A6E924A2F419/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Zhiming_Liu_0-1700447357309.png" alt="Zhiming_Liu_0-1700447357309.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 20 Nov 2023 02:30:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8ULP-Integrate-LPSPI-with-FreeRTOS-ping-pong-example/m-p/1759470#M215927</guid>
      <dc:creator>Zhiming_Liu</dc:creator>
      <dc:date>2023-11-20T02:30:51Z</dc:date>
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