topic Re: Unable to upload code in MIMXRT1024 in i.MX Processors

Unable to upload code in MIMXRT1024

manish_bmpl — Wed, 08 Nov 2023 04:22:04 GMT

Hi,

We have designed a new board, during board bring up we are trying to upload the code, but unable to do so, getting errors. attaching the screen shorts of the same.

Any one can pls let me know the possible causes of this issue.

Thanks in advance.

Regards,

Re: Unable to upload code in MIMXRT1024

diego_charles — Tue, 14 Nov 2023 21:27:30 GMT

Hi @manish_bmpl

Sorry for not getting back to you sooner. Have you been able to find anything else for your investigation?

First easiest thing to do is regain debug access : Set the MCU to boot from serial downloader mode and make a mass erase to the flash. You can do mass erase to internal flash and application programing using our MCUXpresso Secure Provisioning tool. Here is a post on how to recover boards: https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/RT-board-recovery-for-debugger-connect-issues/ta-p/1635260

I have some HW recommendations:

Make sure that the external 24 MHz crystal is providing signal. This crystal is necesary to boot.
Review our Hardware design guide MIMXRT1020HDUG https://www.nxp.com/webapp/Download?colCode=MIMXRT1020HDUG&location=null. Some interesting pointers of this guide are Power Up sequence, DCDC usage and debug connection.The RT10xx default debug interface is the SWD.
Please check if LPUART pins are not powered before the power is applied to the MCU.

All the best,

Diego

Re: Unable to upload code in MIMXRT1024

manish_bmpl — Tue, 21 Nov 2023 13:14:31 GMT

Hi @diego_charles ,

Thanks for the info.

I checked and following are the observations:

1) Not getting 24Mhz clock.

2) Power sequence is OK

3) Not getting DCDC_OUT.

What could be the reason for DCDC_OUT not generating.

Thanks & Regards,

Manish Agarwal

Re: Unable to upload code in MIMXRT1024

diego_charles — Tue, 21 Nov 2023 22:37:48 GMT

Hi @manish_bmpl

Thanks for your response!

The 24 MHz clock signal is critical for the system. Also, the DCDC_OUT, as typically, provides 1.8v to the VDD_SOC_IN pins, which are critical power supply pins. Without them it is likely for the system to fail.

I do not know if you are using DCDC, but if you do for the VDD_SOC_IN pins, please make sure to review your DCDC connection diagram according to your guide. Please specify if you are not using DCDC.

In the same way, check the 24 MHz clock, the system should see oscillation there. If your crystal is broken, try a bypass setting. According to the RM, you can use inject external 24 MHz clock generator signal. See details in 5.4.2 Bypass Configuration (24 MHz) of the IMXRT1020RM.

Do not hesitate to share your findings,
Diego

Re: Unable to upload code in MIMXRT1024

manish_bmpl — Fri, 24 Nov 2023 07:06:45 GMT

Hi @diego_charles ,

I am using DCDC output to power the VDD_SOC_IN (Will share the schematic for your reference), after power up i am able to generate in sequence following

1) VDD_SNVS_IN

2) VDD_HIGH_IN

3) DCDC_IN

4) DCDC_PSWITCH

but DCDC_OUT is not generating.

Also i am able to see 1.1V at XTAL1 but not seeing any oscillations.

Want to know whether due to no power up at VDD_SOC_IN no clock is generating or vice versa i.e. no clock is generating therefore DCDC_OUT is not generating 1.3V.

Attaching power up sequence waveform (1st is VDD_SNVS_IN, 2nd is (DCDC_IN, 3rd is DCDC_PSWITCH, & 4th is POR_B)

Thanks & Regards,

Manish Agarwal

Re: Unable to upload code in MIMXRT1024

manish_bmpl — Tue, 28 Nov 2023 11:32:57 GMT

Hi @diego_charles ,

I have supplied 1.1V externally to VDD_SOC_IN pins , now the clock is generating as well as code is being uploaded.

So what are the probable reasons for DCDC_LP output not generating.

An early response will be highly appreciated.

B Regards,

Manish Agarwal

Re: Unable to upload code in MIMXRT1024

diego_charles — Thu, 30 Nov 2023 04:20:01 GMT

Hi @manish_bmpl

I am very glad to know that you have narrowed down the issue! Could you try to increase RC delay for the DCDC_PSWITCH? I can not say exactly from the scope captures the timing between the DCDC_IN and DCDC_PSWITCH. According to our HDUFG the DCDC_PSWITCH is delayed more than 1ms to switch the internal DCDC on

All the best,

Diego