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    <title>topic Re: i.MX6ULL dual enets failed to work simultaneously in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-dual-enets-failed-to-work-simultaneously/m-p/1749734#M215001</link>
    <description>&lt;P&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;I was double checking the device tree bindings you have shared, and I noticed that in here:&lt;BR /&gt;&lt;BR /&gt;ethphy0: ethernet-phy@2 {&lt;BR /&gt;compatible = "ethernet-phy-ieee802.3-c22";&lt;BR /&gt;reg = &amp;lt;0&amp;gt;;&lt;BR /&gt;};&lt;BR /&gt;&lt;BR /&gt;ethphy1: ethernet-phy@1 {&lt;BR /&gt;compatible = "ethernet-phy-ieee802.3-c22";&lt;BR /&gt;reg = &amp;lt;1&amp;gt;;&lt;BR /&gt;};&lt;BR /&gt;&lt;BR /&gt;Please change the ID number for the first phy, so it looks like this:&lt;BR /&gt;&lt;BR /&gt;ethphy0: ethernet-phy@2 {&lt;BR /&gt;compatible = "ethernet-phy-ieee802.3-c22";&lt;BR /&gt;&lt;STRONG&gt;reg = &amp;lt;2&amp;gt;;&lt;/STRONG&gt;&lt;BR /&gt;};&lt;BR /&gt;&lt;BR /&gt;Please try it and let me know of the results,&lt;BR /&gt;Saludos,&lt;BR /&gt;Aldo.&lt;/P&gt;</description>
    <pubDate>Tue, 31 Oct 2023 18:51:20 GMT</pubDate>
    <dc:creator>AldoG</dc:creator>
    <dc:date>2023-10-31T18:51:20Z</dc:date>
    <item>
      <title>i.MX6ULL dual enets failed to work simultaneously</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-dual-enets-failed-to-work-simultaneously/m-p/1747129#M214762</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;Our customer is using i.MX6ULL to develop their product, and needs two enets to work symultaneously.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;Pins of enet0 an enet1 are configured same as EVK, and enable the enet1 in uboot (v2021.04, linux kernel is L5.4.200) same as enet0 initial code, but enet1 will switch back from up and down.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; Below is the log, can you help to check this problem?&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; Thanks very much.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;----log:&lt;/P&gt;&lt;DIV&gt;eth0 RJ45网口灯情况与eth1的相同&lt;/DIV&gt;&lt;DIV&gt;root@ATK-IMX6U:~# [&amp;nbsp; &amp;nbsp;28.443753] random: nonblocking pool is initialized&lt;/DIV&gt;&lt;DIV&gt;[&amp;nbsp; &amp;nbsp;32.003116] ICM20608 ID = 0XFF&lt;/DIV&gt;&lt;DIV&gt;[&amp;nbsp; &amp;nbsp;36.264418] fec 2188000.ethernet eth1: Link is Up - 100Mbps/Full - flow control rx/tx&lt;/DIV&gt;&lt;DIV&gt;[&amp;nbsp; &amp;nbsp;36.272316] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready&lt;/DIV&gt;&lt;DIV&gt;[&amp;nbsp; &amp;nbsp;38.264169] fec 2188000.ethernet eth1: Link is Down&lt;/DIV&gt;&lt;DIV&gt;[&amp;nbsp; &amp;nbsp;38.347731] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready&lt;/DIV&gt;&lt;DIV&gt;[&amp;nbsp; &amp;nbsp;39.264233] fec 2188000.ethernet eth1: Link is Up - 100Mbps/Full - flow control rx/tx&lt;/DIV&gt;&lt;DIV&gt;[&amp;nbsp; &amp;nbsp;39.272135] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready&lt;/DIV&gt;&lt;DIV&gt;[&amp;nbsp; &amp;nbsp;45.264011] fec 2188000.ethernet eth1: Link is Down&lt;/DIV&gt;&lt;DIV&gt;[&amp;nbsp; &amp;nbsp;45.337306] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready&lt;/DIV&gt;&lt;DIV&gt;[&amp;nbsp; &amp;nbsp;46.264339] fec 2188000.ethernet eth1: Link is Up - 100Mbps/Full - flow control rx/tx&lt;/DIV&gt;&lt;DIV&gt;[&amp;nbsp; &amp;nbsp;46.272237] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready&lt;/DIV&gt;&lt;DIV&gt;[&amp;nbsp; &amp;nbsp;48.264175] fec 2188000.ethernet eth1: Link is Down&lt;/DIV&gt;&lt;DIV&gt;[&amp;nbsp; &amp;nbsp;48.335074] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready&lt;/DIV&gt;&lt;DIV&gt;[&amp;nbsp; &amp;nbsp;50.264338] fec 2188000.ethernet eth1: Link is Up - 10Mbps/Full - flow control rx/tx&lt;/DIV&gt;&lt;DIV&gt;[&amp;nbsp; &amp;nbsp;50.272148] IPv6: ADDRCONF(NETDEV_CHANGE): eth1: link becomes ready&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;root@ATK-IMX6U:~#&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;root@ATK-IMX6U:~#&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;root@ATK-IMX6U:~# ifconfig&lt;/DIV&gt;&lt;DIV&gt;eth0&amp;nbsp; &amp;nbsp; &amp;nbsp; Link encap:Ethernet&amp;nbsp; HWaddr 88:44:86:a4:dd:32&amp;nbsp;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; UP BROADCAST MULTICAST&amp;nbsp; MTU:1500&amp;nbsp; Metric:1&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; RX packets:0 errors:0 dropped:0 overruns:0 frame:0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; TX packets:0 errors:0 dropped:0 overruns:0 carrier:0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; collisions:0 txqueuelen:1000&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; RX bytes:0 (0.0 B)&amp;nbsp; TX bytes:0 (0.0 B)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;eth1&amp;nbsp; &amp;nbsp; &amp;nbsp; Link encap:Ethernet&amp;nbsp; HWaddr 88:6b:33:84:25:6e&amp;nbsp;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; inet6 addr: fe80::8a6b:33ff:fe84:256e/64 Scope:Link&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; UP BROADCAST RUNNING MULTICAST DYNAMIC&amp;nbsp; MTU:1500&amp;nbsp; Metric:1&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; RX packets:162 errors:26 dropped:0 overruns:0 frame:26&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; TX packets:119 errors:0 dropped:0 overruns:0 carrier:0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; collisions:0 txqueuelen:1000&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; RX bytes:14617 (14.2 KiB)&amp;nbsp; TX bytes:22473 (21.9 KiB)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;lo&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; Link encap:Local Loopback&amp;nbsp;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; inet addr:127.0.0.1&amp;nbsp; Mask:255.0.0.0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; inet6 addr: ::1/128 Scope:Host&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; UP LOOPBACK RUNNING&amp;nbsp; MTU:65536&amp;nbsp; Metric:1&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; RX packets:290 errors:0 dropped:0 overruns:0 frame:0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; TX packets:290 errors:0 dropped:0 overruns:0 carrier:0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; collisions:0 txqueuelen:0&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; RX bytes:20072 (19.6 KiB)&amp;nbsp; TX bytes:20072 (19.6 KiB)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;root@ATK-IMX6U:~# [&amp;nbsp; &amp;nbsp;80.264172] fec 2188000.ethernet eth1: Link is Down&lt;/DIV&gt;&lt;DIV&gt;[&amp;nbsp; &amp;nbsp;80.353972] IPv6: ADDRCONF(NETDEV_UP): eth1: link is not ready&lt;/DIV&gt;&lt;DIV&gt;[&amp;nbsp; &amp;nbsp;80.754214] fec 20b4000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx&lt;/DIV&gt;&lt;DIV&gt;[&amp;nbsp; &amp;nbsp;80.762115] IPv6: ADDRCONF(NETDEV_CHANGE): eth0: link becomes ready&lt;/DIV&gt;&lt;DIV&gt;ifconfig&lt;/DIV&gt;&lt;DIV&gt;eth0&amp;nbsp; &amp;nbsp; &amp;nbsp; Link encap:Ethernet&amp;nbsp; HWaddr 88:44:86:a4:dd:32&amp;nbsp;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; inet addr:10.110.110.122&amp;nbsp; Bcast:10.110.110.255&amp;nbsp; Mask:255.255.255.0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; inet6 addr: fe80::8a44:86ff:fea4:dd32/64 Scope:Link&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; UP BROADCAST RUNNING MULTICAST&amp;nbsp; MTU:1500&amp;nbsp; Metric:1&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; RX packets:60 errors:3 dropped:0 overruns:0 frame:3&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; TX packets:49 errors:0 dropped:0 overruns:0 carrier:0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; collisions:0 txqueuelen:1000&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; RX bytes:7545 (7.3 KiB)&amp;nbsp; TX bytes:8890 (8.6 KiB)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;eth1&amp;nbsp; &amp;nbsp; &amp;nbsp; Link encap:Ethernet&amp;nbsp; HWaddr 88:6b:33:84:25:6e&amp;nbsp;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; UP BROADCAST MULTICAST DYNAMIC&amp;nbsp; MTU:1500&amp;nbsp; Metric:1&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; RX packets:186 errors:30 dropped:0 overruns:0 frame:30&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; TX packets:120 errors:0 dropped:0 overruns:0 carrier:0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; collisions:0 txqueuelen:1000&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; RX bytes:16274 (15.8 KiB)&amp;nbsp; TX bytes:23063 (22.5 KiB)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;lo&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; Link encap:Local Loopback&amp;nbsp;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; inet addr:127.0.0.1&amp;nbsp; Mask:255.0.0.0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; inet6 addr: ::1/128 Scope:Host&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; UP LOOPBACK RUNNING&amp;nbsp; MTU:65536&amp;nbsp; Metric:1&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; RX packets:290 errors:0 dropped:0 overruns:0 frame:0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; TX packets:290 errors:0 dropped:0 overruns:0 carrier:0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; collisions:0 txqueuelen:0&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; RX bytes:20072 (19.6 KiB)&amp;nbsp; TX bytes:20072 (19.6 KiB)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;uboot启动后网口提示内容：&lt;/DIV&gt;&lt;DIV&gt;主要能看出找不到 phy&lt;/DIV&gt;&lt;DIV&gt;U-Boot 2021.04-dirty (Oct 25 2023 - 14:44:23 +0800)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;CPU:&amp;nbsp; &amp;nbsp;i.MX6ULL rev1.1 528 MHz (running at 396 MHz)&lt;/DIV&gt;&lt;DIV&gt;CPU:&amp;nbsp; &amp;nbsp;Industrial temperature grade (-40C to 105C) at 49C&lt;/DIV&gt;&lt;DIV&gt;Reset cause: POR&lt;/DIV&gt;&lt;DIV&gt;Model: i.MX6 ULL 14x14 EVK Board&lt;/DIV&gt;&lt;DIV&gt;Board: MX6ULL 14x14 EVK&lt;/DIV&gt;&lt;DIV&gt;DRAM:&amp;nbsp; 512 MiB&lt;/DIV&gt;&lt;DIV&gt;MMC:&amp;nbsp; &amp;nbsp;FSL_SDHC: 0, FSL_SDHC: 1&lt;/DIV&gt;&lt;DIV&gt;Loading Environment from MMC... *** Warning - bad CRC, using default environment&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;[*]-Video Link 0 (480 x 272)&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; [0] lcdif@21c8000, video&lt;/DIV&gt;&lt;DIV&gt;In:&amp;nbsp; &amp;nbsp; serial&lt;/DIV&gt;&lt;DIV&gt;Out:&amp;nbsp; &amp;nbsp;serial&lt;/DIV&gt;&lt;DIV&gt;Err:&amp;nbsp; &amp;nbsp;serial&lt;/DIV&gt;&lt;DIV&gt;switch to partitions #0, OK&lt;/DIV&gt;&lt;DIV&gt;mmc1(part 0) is current device&lt;/DIV&gt;&lt;DIV&gt;flash target is MMC:1&lt;/DIV&gt;&lt;DIV&gt;Net:&amp;nbsp; &amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Error: ethernet@20b4000 address not set.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Error: ethernet@20b4000 address not set.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Error: ethernet@20b4000 address not set.&lt;/DIV&gt;&lt;DIV&gt;FEC: can't find phy-handle&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Error: ethernet@20b4000 address not set.&lt;/DIV&gt;&lt;DIV&gt;Could not get PHY for FEC0: addr 2&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Error: ethernet@20b4000 address not set.&lt;/DIV&gt;&lt;DIV&gt;FEC: can't find phy-handle&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;Error: ethernet@20b4000 address not set.&lt;/DIV&gt;&lt;DIV&gt;Could not get PHY for FEC0: addr 2&lt;/DIV&gt;&lt;DIV&gt;No ethernet found.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;uboot设备树对两个网口的配置：&lt;/DIV&gt;&lt;DIV&gt;&amp;amp;fec1 {&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;pinctrl-names = "default";&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;// pinctrl-0 = &amp;lt;&amp;amp;pinctrl_enet1&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;pinctrl-0 = &amp;lt;&amp;amp;pinctrl_enet1 &amp;amp;pinctrl_enet1_reset&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;phy-mode = "rmii";&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;phy-handle = &amp;lt;&amp;amp;ethphy0&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;phy-reset-gpios = &amp;lt;&amp;amp;gpio5 7 GPIO_ACTIVE_LOW&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;phy-reset-duration = &amp;lt;200&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;status = "okay";&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;};&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;amp;fec2 {&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;pinctrl-names = "default";&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;// pinctrl-0 = &amp;lt;&amp;amp;pinctrl_enet2&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;pinctrl-0 = &amp;lt;&amp;amp;pinctrl_enet2 &amp;amp;pinctrl_enet2_reset&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;phy-mode = "rmii";&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;phy-handle = &amp;lt;&amp;amp;ethphy1&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;phy-reset-gpios = &amp;lt;&amp;amp;gpio5 8 GPIO_ACTIVE_LOW&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; phy-reset-duration = &amp;lt;200&amp;gt;;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;status = "okay";&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;mdio {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#address-cells = &amp;lt;1&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#size-cells = &amp;lt;0&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ethphy0: ethernet-phy@2 {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;reg = &amp;lt;2&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;micrel,led-mode = &amp;lt;1&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;clocks = &amp;lt;&amp;amp;clks IMX6UL_CLK_ENET_REF&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;clock-names = "rmii-ref";&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ethphy1: ethernet-phy@1 {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;reg = &amp;lt;1&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;micrel,led-mode = &amp;lt;1&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;clocks = &amp;lt;&amp;amp;clks IMX6UL_CLK_ENET2_REF&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;clock-names = "rmii-ref";&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;};&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;/*enet1 reset zuozhongkai*/&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;pinctrl_enet1_reset: enet1resetgrp {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; fsl,pins = &amp;lt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* used for enet1&amp;nbsp; reset */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07&amp;nbsp; &amp;nbsp; &amp;nbsp; 0x10B0&amp;nbsp; &amp;nbsp; &amp;nbsp; /* ENET1 RESET */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;gt;;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; };&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;/*enet2 reset zuozhongkai*/&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;pinctrl_enet2_reset: enet2resetgrp {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; fsl,pins = &amp;lt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* used for enet2&amp;nbsp; reset */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08&amp;nbsp; &amp;nbsp; &amp;nbsp; 0x10B0&amp;nbsp; &amp;nbsp; &amp;nbsp;/* ENET2 RESET */&amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;gt;;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; };&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;pinctrl_enet1: enet1grp {&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; fsl,pins = &amp;lt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 0x1b0b0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 0x1b0b0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 0x1b0b0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 0x1b0b0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 0x1b0b0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 0x1b0b0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 0x1b0b0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 0x4001b031&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /* MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x10b0 */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;gt;;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; };&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; pinctrl_enet2: enet2grp {&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; fsl,pins = &amp;lt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_GPIO1_IO07__ENET2_MDC&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 0x1b0b0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_GPIO1_IO06__ENET2_MDIO&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 0x1b0b0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 0x1b0b0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 0x1b0b0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 0x1b0b0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 0x1b0b0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 0x1b0b0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 0x1b0b0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 0x1b0b0&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; 0x4001b031&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; /*MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x10b0 */&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b009&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;gt;;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; };&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;内核设备树对网口的配置除了fec的配置不相同其余都相同：&lt;/DIV&gt;&lt;DIV&gt;&amp;amp;fec1 {&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;pinctrl-names = "default";&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;pinctrl-0 = &amp;lt;&amp;amp;pinctrl_enet1&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;amp;pinctrl_enet1_reset&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;phy-mode = "rmii";&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;phy-handle = &amp;lt;&amp;amp;ethphy0&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;phy-reset-gpios = &amp;lt;&amp;amp;gpio5 7 GPIO_ACTIVE_LOW&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;phy-reset-duration = &amp;lt;200&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;status = "okay";&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;};&lt;/DIV&gt;&lt;DIV&gt;/*ETH1:恢复双网口，且共用一个reset引脚 2023-06-14 */&lt;/DIV&gt;&lt;DIV&gt;&amp;amp;fec2 {&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;pinctrl-names = "default";&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;pinctrl-0 = &amp;lt;&amp;amp;pinctrl_enet2&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;&amp;amp;pinctrl_enet2_reset&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;phy-mode = "rmii";&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;phy-handle = &amp;lt;&amp;amp;ethphy1&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;phy-reset-gpios = &amp;lt;&amp;amp;gpio5 8 GPIO_ACTIVE_LOW&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;phy-reset-duration = &amp;lt;200&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;status = "okay";&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;mdio {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#address-cells = &amp;lt;1&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;#size-cells = &amp;lt;0&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ethphy0: ethernet-phy@2 {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;compatible = "ethernet-phy-ieee802.3-c22";&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;reg = &amp;lt;0&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ethphy1: ethernet-phy@1 {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;compatible = "ethernet-phy-ieee802.3-c22";&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;reg = &amp;lt;1&amp;gt;;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;};&lt;/DIV&gt;</description>
      <pubDate>Thu, 26 Oct 2023 13:52:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-dual-enets-failed-to-work-simultaneously/m-p/1747129#M214762</guid>
      <dc:creator>jimmyli</dc:creator>
      <dc:date>2023-10-26T13:52:36Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6ULL dual enets failed to work simultaneously</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-dual-enets-failed-to-work-simultaneously/m-p/1748012#M214848</link>
      <description>&lt;P&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;Could you share the full part number of the i.MX that you're using?&lt;BR /&gt;Please note that only MCIMX6Y2xxxxxxx can support 2 Ethernet Ifs.&lt;BR /&gt;&lt;BR /&gt;Saludos,&lt;BR /&gt;Aldo.&lt;/P&gt;</description>
      <pubDate>Fri, 27 Oct 2023 20:08:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-dual-enets-failed-to-work-simultaneously/m-p/1748012#M214848</guid>
      <dc:creator>AldoG</dc:creator>
      <dc:date>2023-10-27T20:08:20Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6ULL dual enets failed to work simultaneously</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-dual-enets-failed-to-work-simultaneously/m-p/1748172#M214862</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;The full part No. is&amp;nbsp;MCIMX6Y2CVM05AB.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; Yes. As mentioned above, we are trying to enable two ENETs. Offical bsp only enable ENET0, so we try to enable another ENET1, but fail.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp;Thanks very much.&lt;/P&gt;</description>
      <pubDate>Mon, 30 Oct 2023 00:36:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-dual-enets-failed-to-work-simultaneously/m-p/1748172#M214862</guid>
      <dc:creator>jimmyli</dc:creator>
      <dc:date>2023-10-30T00:36:03Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6ULL dual enets failed to work simultaneously</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-dual-enets-failed-to-work-simultaneously/m-p/1749734#M215001</link>
      <description>&lt;P&gt;Hello,&lt;BR /&gt;&lt;BR /&gt;I was double checking the device tree bindings you have shared, and I noticed that in here:&lt;BR /&gt;&lt;BR /&gt;ethphy0: ethernet-phy@2 {&lt;BR /&gt;compatible = "ethernet-phy-ieee802.3-c22";&lt;BR /&gt;reg = &amp;lt;0&amp;gt;;&lt;BR /&gt;};&lt;BR /&gt;&lt;BR /&gt;ethphy1: ethernet-phy@1 {&lt;BR /&gt;compatible = "ethernet-phy-ieee802.3-c22";&lt;BR /&gt;reg = &amp;lt;1&amp;gt;;&lt;BR /&gt;};&lt;BR /&gt;&lt;BR /&gt;Please change the ID number for the first phy, so it looks like this:&lt;BR /&gt;&lt;BR /&gt;ethphy0: ethernet-phy@2 {&lt;BR /&gt;compatible = "ethernet-phy-ieee802.3-c22";&lt;BR /&gt;&lt;STRONG&gt;reg = &amp;lt;2&amp;gt;;&lt;/STRONG&gt;&lt;BR /&gt;};&lt;BR /&gt;&lt;BR /&gt;Please try it and let me know of the results,&lt;BR /&gt;Saludos,&lt;BR /&gt;Aldo.&lt;/P&gt;</description>
      <pubDate>Tue, 31 Oct 2023 18:51:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-dual-enets-failed-to-work-simultaneously/m-p/1749734#M215001</guid>
      <dc:creator>AldoG</dc:creator>
      <dc:date>2023-10-31T18:51:20Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6ULL dual enets failed to work simultaneously</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-dual-enets-failed-to-work-simultaneously/m-p/1749869#M215014</link>
      <description>&lt;P&gt;Dear Aldo,&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; Thanks very much for your help.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; We will try again.&lt;/P&gt;</description>
      <pubDate>Wed, 01 Nov 2023 01:17:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-dual-enets-failed-to-work-simultaneously/m-p/1749869#M215014</guid>
      <dc:creator>jimmyli</dc:creator>
      <dc:date>2023-11-01T01:17:20Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6ULL dual enets failed to work simultaneously</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-dual-enets-failed-to-work-simultaneously/m-p/1752852#M215310</link>
      <description>&lt;P&gt;&lt;FONT&gt;Dear&amp;nbsp; AIdoG，&lt;/FONT&gt;&lt;/P&gt;&lt;P&gt;Following your instructions, I made modifications to my kernel device tree and successfully assigned IP addresses to two network interfaces. It could be due to both interfaces sharing a single PHY chip on the hardware. After conducting my tests, I observed that eth1 needs to be brought up and assigned an IP address first. Only then can eth0 obtain an IP address via dhclient. Additionally, when I bring down either eth1 or eth0, the other interface is also set to "DOWN" at the data link layer. For detailed information, please refer to my log files.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 06 Nov 2023 13:26:12 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-dual-enets-failed-to-work-simultaneously/m-p/1752852#M215310</guid>
      <dc:creator>xisuisan</dc:creator>
      <dc:date>2023-11-06T13:26:12Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX6ULL dual enets failed to work simultaneously</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-dual-enets-failed-to-work-simultaneously/m-p/1752955#M215323</link>
      <description>&lt;P&gt;Hi,&lt;BR /&gt;&lt;BR /&gt;Please do help me creating a new thread.&lt;/P&gt;&lt;P&gt;Also, please share the device tree and the changes you made.&lt;BR /&gt;&lt;BR /&gt;Thank you,&lt;BR /&gt;Saludos,&lt;BR /&gt;Aldo.&lt;/P&gt;</description>
      <pubDate>Mon, 06 Nov 2023 17:13:10 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-dual-enets-failed-to-work-simultaneously/m-p/1752955#M215323</guid>
      <dc:creator>AldoG</dc:creator>
      <dc:date>2023-11-06T17:13:10Z</dc:date>
    </item>
    <item>
      <title>回复： i.MX6ULL dual enets failed to work simultaneously</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-dual-enets-failed-to-work-simultaneously/m-p/1755838#M215581</link>
      <description>&lt;P&gt;U-Boot version: lf_v2021.04 Kernel version: 5.4.200 Note: On my development board, eth0 and eth1 share a common PHY chip!&lt;/P&gt;&lt;P&gt;The modifications I made are as follows:&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;&lt;P&gt;Restored the network interface pin configuration in the U-Boot device tree without modifying the U-Boot device tree.&lt;/P&gt;&lt;/LI&gt;&lt;LI&gt;&lt;P&gt;Made the following modifications to the device tree in the kernel:&lt;/P&gt;&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;SPAN&gt;ethphy0: ethernet-phy@2 {&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;compatible = "ethernet-phy-ieee802.3-c22";&lt;/SPAN&gt;&lt;BR /&gt;&lt;STRONG&gt;reg = &amp;lt;2&amp;gt;;&lt;/STRONG&gt;&lt;BR /&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Sat, 11 Nov 2023 09:36:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX6ULL-dual-enets-failed-to-work-simultaneously/m-p/1755838#M215581</guid>
      <dc:creator>xisuisan</dc:creator>
      <dc:date>2023-11-11T09:36:20Z</dc:date>
    </item>
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