topic Re: imx8mp in i.MX Processors

imx8mp

chenchenchen — Wed, 02 Nov 2022 06:19:34 GMT

Hello:

I have a question.

pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
>;
};

I see that the i2c1_scl config value is 0x400001c3.

as we know that the I2Cn_SCL and I2Cn_SDA signals must

have open-drain or open-collector outputs.

I see that the config value is 0x400001c3, the ODE bit is disabled. shouldn't this bit is enable?

Thanks

Re: imx8mp

joanxie — Fri, 11 Nov 2022 06:20:01 GMT

you don't need set this ODE bit, you just keep it as dts file default settings

Re: imx8mp

sveitola — Wed, 18 Oct 2023 10:01:28 GMT

Hello, I have a related question.

Does the FSEL field have any effect on the I2C setting? Our design is violating the I2C fall time specification and we would like to ensure that the slew rate is slow.