i.MX6 EIM Asynchronous Timing

mlu — Sun, 03 Feb 2013 19:19:31 GMT

I am trying to program EIM CS0 for non-multiplexed asynchronous access to CPLD-based registers, but I cannot program proper timing of CS, OE, ADV, etc unless I understand when the processor samples data from the data bus during a read cycle. I have read the EIM section of the IMX6DQ Reference Manual, but did not find the answer. When during an asynchronous read cycle does the i.MX6 latch data from the data bus?

Re: i.MX6 EIM Asynchronous Timing

LinWang — Thu, 28 Mar 2013 01:35:21 GMT

Hi Mike,

Please share your schematic first, let's double check if connections are correct.

Thanks!

Lin

topic Re: i.MX6 EIM Asynchronous Timing in i.MX Processors

i.MX6 EIM Asynchronous Timing

Re: i.MX6 EIM Asynchronous Timing