i.MX ProcessorsのトピックRe: IMX8mn wakeup patch for 6.1.22 kernel

IMX8mn wakeup patch for 6.1.22 kernel

k_specka — Thu, 12 Oct 2023 09:27:32 GMT

Hello, I'm trying to get the wakeup from M4 to A53 running.

As far that I know there are 3 patches needed.

1st in the M4 code to use 'MU_TriggerInterrupts(MUB, kMU_GenInt0InterruptTrigger);'
2nd the ATF-M4-run patch witch changes on pll_override struct that can easily ported from older patches.
And 3rd the GIR-wakeup patch

Actual I only found the GIR patches for older kernel but the code in the actual yocto using the 6.1.22 kernel seems to be different.

Are there patches available for the actual yocto?
Or what is needed to get the wakeup running?

Actual deep sleep is working and M4 still running - but can't wakeup the A53

Re: IMX8mn wakeup patch for 6.1.22 kernel

Sanket_Parekh — Thu, 12 Oct 2023 12:04:05 GMT

Hello @k_specka,

I hope you are doing well.

For Linux BSP 5.4, it is available, I have shared a link for reference, one can refer to that.
https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/M4-Low-Power-Demo-on-i-MX8MM/ta-p/1101109

I hope it helps!

Thanks & Regards,
Sanket Parekh

Re: IMX8mn wakeup patch for 6.1.22 kernel

k_specka — Thu, 12 Oct 2023 12:44:52 GMT

Yes, I have already seen this. So is the recommended way to go back to the i.MX 5.4 Beta release L5.4.24_2.1.0?
Or is there a known way to get the wakeup running on LF6.1.22_2.0.0? Because the code to place the GIR patch looks much different.

Re: IMX8mn wakeup patch for 6.1.22 kernel

Sanket_Parekh — Fri, 13 Oct 2023 03:09:19 GMT

Hello @k_specka,

I hope you are doing well.

"So is the recommended way to go back to the i.MX 5.4 Beta release L5.4.24_2.1.0?"
->Yes.

Thanks & Regards,
Sanket Parekh

Re: IMX8mn wakeup patch for 6.1.22 kernel

k_specka — Wed, 08 Nov 2023 09:21:11 GMT

For 6.1.22 I'm using the following patch for the GIR-wakeup, just ignoring the unused defines from the original and wakeup is working fine.

--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -260,7 +260,8 @@ static int imx_mu_generic_rxdb(struct imx_mu_priv *priv,
{
imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx),
priv->dcfg->xSR[IMX_MU_GSR]);
- mbox_chan_received_data(cp->chan, NULL);
+ if (cp->chan->cl)
+ mbox_chan_received_data(cp->chan, NULL);

return 0;
}
@@ -867,6 +868,18 @@ static int imx_mu_probe(struct platform_device *pdev)
return ret;
}

+ /* TY: Enable GIR wakeup { */
+ dev_info(dev, "enable wakeup GIE bit\n");
+ {
+ struct mbox_chan *chan;
+
+ /* TYPE: 3, Index: 0, 3 * 4 + 1 = 0 */
+ chan = &priv->mbox.chans[12];
+ chan->cl = NULL;
+ imx_mu_startup(chan);
+ }
+ /* } TY: Enable GIR wakeup */
+
pm_runtime_enable(dev);

ret = pm_runtime_resume_and_get(dev);
--

And the following for the atf-m4-run:

--- a/plat/imx/imx8m/gpc_common.c
+++ b/plat/imx/imx8m/gpc_common.c
@@ -20,7 +20,7 @@
#include <plat_imx8.h>
#include <imx_rdc.h>

-#define MAX_PLL_NUM U(10)
+#define MAX_PLL_NUM U(8)

static uint32_t gpc_imr_offset[] = { IMR1_CORE0_A53, IMR1_CORE1_A53, IMR1_CORE2_A53, IMR1_CORE3_A53, };

@@ -316,8 +316,6 @@ struct pll_override pll[MAX_PLL_NUM] = {
{.reg = 0x50, .override_mask = (1 << 12) | (1 << 8), },
{.reg = 0x64, .override_mask = (1 << 10) | (1 << 8), },
{.reg = 0x74, .override_mask = (1 << 10) | (1 << 8), },
- {.reg = 0x84, .override_mask = (1 << 10) | (1 << 8), },
- {.reg = 0x94, .override_mask = 0x5555500, },
{.reg = 0x104, .override_mask = 0x5555500, },
{.reg = 0x114, .override_mask = 0x500, },
};
--

Re: IMX8mn wakeup patch for 6.1.22 kernel

Sanket_Parekh — Thu, 09 Nov 2023 02:55:15 GMT

Hello @k_specka,

I hope you are doing well.

Thanks for sharing the patch, I'm glad it works for you!
Hence the issue is solved, Can I mark this case as closed?

Thanks & Regards,
Sanket Parekh