Interrupt geneartion between Cortex-A53 & Cortex-M4 in imx8mm

prasannakulkarni — Fri, 15 Sep 2023 04:44:14 GMT

I too have similar question!!, what is the purpose of keeping M4 along with Cortex -A53 in imx8mmini or so? What are the best examples

which have been already implemented using these cores ?

I was going though Reference manual of imx8m Message Unit Section, explains about so many concepts, but are there any examples to verify those? I want to send an interrupt from M4 to A53 or vice versa by making use of below concepts. I could find very few examples in mcuexpress sdk that too simple messaging examples.... is OpenAmp supported on imx8m platform? or only RPmsglite works?

4.3.2.7.1 Interrupts to the Processors
There are 12 interrupt sources from the MU to the Processors:
• Four receive interrupts (asserted when the Processors receive full bits are set and
enabled in the xCR register) for each of the receive registers
• Four transmit interrupts (asserted when the Processor transmit empty bits are set and
enabled in the xCR register) for each of the transmit registers
• Four general purpose interrupts (asserted when the GIP bits are set and enabled in the
xCR register)

kindly update

Re: Interrupt geneartion between Cortex-A53 & Cortex-M4 in imx8mm

Zhiming_Liu — Wed, 20 Sep 2023 02:46:07 GMT

The Linux side will call imx_rproc_xtr_mbox_init->mbox_request_channel_byname->mbox_request_channel->imx_mu_dcfg to realize RX/TX message, but the mailbox driver miss the code for Generic interrupt, you can refer this case : https://community.nxp.com/t5/i-MX-Processors/imx8mm-Wake-Linux-from-M4-core/m-p/1492800

topic Re: Interrupt geneartion between Cortex-A53 & Cortex-M4 in imx8mm in i.MX Processors

Interrupt geneartion between Cortex-A53 & Cortex-M4 in imx8mm

Re: Interrupt geneartion between Cortex-A53 & Cortex-M4 in imx8mm