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    <title>i.MX ProcessorsのトピックRe: IMX8MP ENET_QOS RGMII REF CLOCK</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MP-ENET-QOS-RGMII-REF-CLOCK/m-p/1723479#M212628</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/172272"&gt;@Jerry_H&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;For EQOS CLOCK mapping, you can choose EXT_CLK_4 if you want to use external clock.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Zhiming_Liu_0-1694738244366.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/241105i2FB5DE1660C4F0D7/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Zhiming_Liu_0-1694738244366.png" alt="Zhiming_Liu_0-1694738244366.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;But in evk dtsi, eqos is using SYS_PLL1 and SYS_PLL2.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Zhiming_Liu_1-1694738302087.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/241106i5CDC701B5B183D15/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Zhiming_Liu_1-1694738302087.png" alt="Zhiming_Liu_1-1694738302087.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;There is no clock name like ENET_QOS_REF_XXX, maybe the&amp;nbsp;ENET_QOS_TIMER_CLK_ROOT is your need.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Zhiming_Liu_2-1694738649843.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/241107iF4BF71A1A80D0AC1/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Zhiming_Liu_2-1694738649843.png" alt="Zhiming_Liu_2-1694738649843.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;Best Regards&lt;/P&gt;
&lt;P&gt;Zhiming&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Fri, 15 Sep 2023 00:45:25 GMT</pubDate>
    <dc:creator>Zhiming_Liu</dc:creator>
    <dc:date>2023-09-15T00:45:25Z</dc:date>
    <item>
      <title>IMX8MP ENET_QOS RGMII REF CLOCK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MP-ENET-QOS-RGMII-REF-CLOCK/m-p/1721692#M212506</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;we are trying to use ENET1 and ENET_QOS on IMX8MP.&lt;/P&gt;&lt;P&gt;For ENET1 the REF_CLOCK is listed in the signal mapping as GPIO1_IO00.&lt;/P&gt;&lt;P&gt;When I now look for the signal mapping for ENET_QOS there is no such pin defined.&lt;/P&gt;&lt;P&gt;Do I have to share the ENET1 clock signal using a clock buffer or are there any other pins use?&lt;/P&gt;&lt;P&gt;ENET1 and ENET_QOS should run in RGMII mode.&lt;/P&gt;&lt;P&gt;Any hints where to get this signal from?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Kind regards.&lt;/P&gt;</description>
      <pubDate>Wed, 13 Sep 2023 06:08:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8MP-ENET-QOS-RGMII-REF-CLOCK/m-p/1721692#M212506</guid>
      <dc:creator>Jerry_H</dc:creator>
      <dc:date>2023-09-13T06:08:22Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8MP ENET_QOS RGMII REF CLOCK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8MP-ENET-QOS-RGMII-REF-CLOCK/m-p/1723479#M212628</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/172272"&gt;@Jerry_H&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;For EQOS CLOCK mapping, you can choose EXT_CLK_4 if you want to use external clock.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Zhiming_Liu_0-1694738244366.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/241105i2FB5DE1660C4F0D7/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Zhiming_Liu_0-1694738244366.png" alt="Zhiming_Liu_0-1694738244366.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;But in evk dtsi, eqos is using SYS_PLL1 and SYS_PLL2.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Zhiming_Liu_1-1694738302087.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/241106i5CDC701B5B183D15/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Zhiming_Liu_1-1694738302087.png" alt="Zhiming_Liu_1-1694738302087.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;There is no clock name like ENET_QOS_REF_XXX, maybe the&amp;nbsp;ENET_QOS_TIMER_CLK_ROOT is your need.&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Zhiming_Liu_2-1694738649843.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/241107iF4BF71A1A80D0AC1/image-size/medium?v=v2&amp;amp;px=400" role="button" title="Zhiming_Liu_2-1694738649843.png" alt="Zhiming_Liu_2-1694738649843.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;Best Regards&lt;/P&gt;
&lt;P&gt;Zhiming&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 15 Sep 2023 00:45:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8MP-ENET-QOS-RGMII-REF-CLOCK/m-p/1723479#M212628</guid>
      <dc:creator>Zhiming_Liu</dc:creator>
      <dc:date>2023-09-15T00:45:25Z</dc:date>
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