imx8mp display ordering

NathanG — Tue, 05 Sep 2023 15:57:55 GMT

Hello,

I have a Variscite IMX8MP-SOM on a custom board running Kernel 5.10.72 and Android 11.0.0_2.6.0

Multidisplay output is working with DSI -> sn65dsi84 -> lvds (1024x600) and a second lvds panel on lvds channel 1 (1280x800). However, I need the native LVDS panel to be primary instead of the DSI output. When I swap lcdif1 and lcdif2 in the display-subsystem devicetree node, both crtc initialize in the reversed order as expected, but the lcdifv3 set mode is only called for the lvds display and the second backlight remains disabled.

Is there a patch from a later kernel needed? Or am I missing another device tree change?

Normal log (with additional diagnostic prints):

display-subsystem { compatible = "fsl,imx-display-subsystem"; ports = <&lcdif1_disp>, <&lcdif2_disp>, <&lcdif3_disp>; };

[ 2.819798][ T1] imx-lcdifv3-crtc imx-lcdifv3-crtc.0: lcdifv3_crtc_probe: lcdifv3 crtc probe begin
[ 2.829735][ T1] imx-lcdifv3-crtc imx-lcdifv3-crtc.1: lcdifv3_crtc_probe: lcdifv3 crtc probe begin
[ 2.842626][ T1] imx-lcdifv3-crtc imx-lcdifv3-crtc.0: lcdifv3_crtc_bind: lcdifv3 crtc bind begin
[ 2.851786][ T1] imx-lcdifv3-crtc imx-lcdifv3-crtc.0: lcdifv3_crtc_bind: lcdifv3 crtc bind end
[ 2.860692][ T1] imx-drm display-subsystem: bound imx-lcdifv3-crtc.0 (ops lcdifv3_crtc_ops [imx_lcdifv3_crtc])
[ 2.870968][ T1] imx-lcdifv3-crtc imx-lcdifv3-crtc.1: lcdifv3_crtc_bind: lcdifv3 crtc bind begin
[ 2.880061][ T1] imx-lcdifv3-crtc imx-lcdifv3-crtc.1: lcdifv3_crtc_bind: lcdifv3 crtc bind end
[ 2.888960][ T1] imx-drm display-subsystem: bound imx-lcdifv3-crtc.1 (ops lcdifv3_crtc_ops [imx_lcdifv3_crtc])
[ 2.899313][ T1] imx_sec_dsim_drv 32e60000.mipi_dsi: version number is 0x1060200
[ 2.907231][ T1] imx_sec_dsim_drv 32e60000.mipi_dsi: Lanes 4 channel 0 format 0 mode 3
[ 2.915462][ T1] imx-drm display-subsystem: bound 32e60000.mipi_dsi (ops imx_sec_dsim_ops [sec_mipi_dsim_imx])
[ 2.925954][ T1] imx-drm display-subsystem: bound 32c00000.bus:ldb@32ec005c (ops imx8mp_ldb_ops [imx8mp_ldb])
[ 2.936502][ T1] [drm] Initialized imx-drm 1.0.0 20120507 for display-subsystem on minor 0
[ 2.948721][ T1] imx-drm display-subsystem: [drm] fb0: imx-drmdrmfb frame buffer device

[ 12.202392][ T351] *** lcdifv3 set mode
[ 12.206423][ T351] *** h: 1024 v: 600 reg: 39322624
[ 12.211438][ T351] *** h fp: 160 h_bp: 158 reg: 10354848
[ 12.216877][ T351] *** v fp: 12 v_bp: 21 reg: 1376268
[ 12.222051][ T351] *** h_sync: 2 v_sync: 2 reg: 131074
[ 12.238715][ T351] imx_sec_dsim_drv 32e60000.mipi_dsi: DSIM resolution: 2580400
[ 12.246252][ T351] imx_sec_dsim_drv 32e60000.mipi_dsi: DSIM Vporch: C0015
[ 12.253215][ T351] imx_sec_dsim_drv 32e60000.mipi_dsi: DSIM Hporch: 720071
[ 12.260279][ T351] imx_sec_dsim_drv 32e60000.mipi_dsi: DSIM sync: 800002
[ 12.267143][ T351] imx_sec_dsim_drv 32e60000.mipi_dsi: DSIM FLAGS: 3
[ 12.273636][ T351] imx_sec_dsim_drv 32e60000.mipi_dsi: DSI CONFIG: 600707F
[ 12.281886][ T351] imx_sec_dsim_drv 32e60000.mipi_dsi: DSIM timing 1: 20D0803
[ 12.289188][ T351] imx_sec_dsim_drv 32e60000.mipi_dsi: DSIM timing 2: 30305
[ 12.297356][ T351] imx_sec_dsim_drv 32e60000.mipi_dsi: DSIM clocks: 91F80002
[ 12.304542][ T351] fefr: sn65dsi83_atomic_enable bridge_state->output_bus_cfg.format=1011
[ 12.312858][ T351] sn65dsi85 start: 1184 end: 1186 display: 1024 total 1344
[ 12.320048][ T351] sn65dsi85 name: 1024x600
...
[ 17.719890][ T351] *** lcdifv3 set mode
[ 17.732786][ T351] *** h: 1280 v: 800 reg: 52430080
[ 17.737830][ T351] *** h fp: 80 h_bp: 80 reg: 5242960
[ 17.743033][ T351] *** v fp: 11 v_bp: 12 reg: 786443
[ 17.748125][ T351] *** h_sync: 2 v_sync: 2 reg: 131074

Swapped:

display-subsystem { compatible = "fsl,imx-display-subsystem"; ports = <&lcdif2_disp>, <&lcdif1_disp>, <&lcdif3_disp>; };

[ 3.420878][ T1] imx-lcdifv3-crtc imx-lcdifv3-crtc.0: lcdifv3_crtc_probe: lcdifv3 crtc probe begin
[ 3.430813][ T1] imx-lcdifv3-crtc imx-lcdifv3-crtc.1: lcdifv3_crtc_probe: lcdifv3 crtc probe begin
[ 3.443944][ T1] imx-lcdifv3-crtc imx-lcdifv3-crtc.1: lcdifv3_crtc_bind: lcdifv3 crtc bind begin
[ 3.453095][ T1] imx-lcdifv3-crtc imx-lcdifv3-crtc.1: lcdifv3_crtc_bind: lcdifv3 crtc bind end
[ 3.462059][ T1] imx-drm display-subsystem: bound imx-lcdifv3-crtc.1 (ops lcdifv3_crtc_ops [imx_lcdifv3_crtc])
[ 3.472347][ T1] imx-lcdifv3-crtc imx-lcdifv3-crtc.0: lcdifv3_crtc_bind: lcdifv3 crtc bind begin
[ 3.481446][ T1] imx-lcdifv3-crtc imx-lcdifv3-crtc.0: lcdifv3_crtc_bind: lcdifv3 crtc bind end
[ 3.490342][ T1] imx-drm display-subsystem: bound imx-lcdifv3-crtc.0 (ops lcdifv3_crtc_ops [imx_lcdifv3_crtc])
[ 3.500874][ T1] imx-drm display-subsystem: bound 32c00000.bus:ldb@32ec005c (ops imx8mp_ldb_ops [imx8mp_ldb])
[ 3.511093][ T1] imx_sec_dsim_drv 32e60000.mipi_dsi: sec-dsim bridge bind begin
[ 3.518728][ T1] imx_sec_dsim_drv 32e60000.mipi_dsi: version number is 0x1060200
[ 3.526581][ T1] imx_sec_dsim_drv 32e60000.mipi_dsi: Lanes 4 channel 0 format 0 mode 3
[ 3.534792][ T1] imx_sec_dsim_drv 32e60000.mipi_dsi: sec-dsim bridge bind end
[ 3.542218][ T1] imx-drm display-subsystem: bound 32e60000.mipi_dsi (ops imx_sec_dsim_ops [sec_mipi_dsim_imx])
[ 3.552855][ T1] [drm] Initialized imx-drm 1.0.0 20120507 for display-subsystem on minor 0
[ 3.565880][ T1] imx-drm display-subsystem: [drm] fb0: imx-drmdrmfb frame buffer device

[ 15.420957][ T396] *** lcdifv3 set mode
[ 15.424927][ T396] *** h: 1280 v: 800 reg: 52430080
[ 15.429938][ T396] *** h fp: 80 h_bp: 80 reg: 5242960
[ 15.435117][ T396] *** v fp: 11 v_bp: 12 reg: 786443
[ 15.440218][ T396] *** h_sync: 2 v_sync: 2 reg: 131074

Thank you,

Nathan

Re: imx8mp display ordering

brian14 — Thu, 07 Sep 2023 19:37:37 GMT

Hi @NathanG,

It seems that you could apply a patch to implement your multidisplay. However, your Android software is supported by Variscite.
Please contact with the Variscite support team to find the proper solution.

Have a great day!

Re: imx8mp display ordering

NathanG — Thu, 07 Sep 2023 19:46:29 GMT

Hi,

Thanks for the response. The displays work fine in the normal order so this seemed like a low lever driver issue as opposed to a a hardware implementation and the i.mx8m plus seems to have a unique graphics subsystem, which is why I pinged here first.

Further data: Both the LVDS and DSI displays show up in /sys/class//drm/ as card0-LVDS-1 and card0-LVDS-2, but the DSI->bridge->LVDS under card0-LVDS-2 reports disabled for 'cat enabled' and connected for 'cat status'.

Thank you,

Nathan

Re: imx8mp display ordering

NathanG — Thu, 21 Sep 2023 12:06:27 GMT

Hi,

To close the loop, the issue was with the i.MX8M Plus specific ldb initialization file imx8mp-ldb.c . There was a patch applied to the lf-5.10.y branch in October 2022 that was not in the Variscite distribution. This bug also impacts LVDS + HDMI if only Channel 1 is enabled.

https://github.com/nxp-imx/linux-imx/commit/bb87c960d81513dd89f29be363e33fa947211ab2

Nathan

topic Re: imx8mp display ordering in i.MX Processors

imx8mp display ordering

Re: imx8mp display ordering

Re: imx8mp display ordering

Re: imx8mp display ordering