topic QSPI IMX8MP CortexM7 DMA in i.MX Processors

QSPI IMX8MP CortexM7 DMA

Stan88 — Thu, 07 Sep 2023 16:06:27 GMT

Good day.

I'm implementing communication for CortexM7 IMX8MP and FPGA via QSPI. I've ported fsl_flexspi and fsl_flexspi_edma from IMX RT family. Then I changed EDMA to SDMA, because realization of EDMA is very different. When I using FLEXSPI_TransferBlocking() method everything works fine. But when I change it to FLEXSPI_TransferSDMA() - I can see CMD, ADDR and then no data and clocks, but CS signal steel in low state:

Here is my SDMA transfering:

/* Prepare transfer. */
SDMA_PrepareTransfer(&xferConfig, (uint32_t)xfer->data, (uint32_t)&base->TFDR[0], (uint32_t)handle->nsize, (uint32_t)handle->nsize, (uint32_t)handle->nbytes,
(uint32_t)xfer->dataSize, 36U, kSDMA_PeripheralNormal, kSDMA_MemoryToPeripheral);

/* Submit transfer. */
SDMA_SubmitTransfer(handle->txSdmaHandle, &xferConfig);
SDMA_SetCallback(handle->txSdmaHandle, FLEXSPI_TransferSDMACallback,
&s_sdmaPrivateHandle[FLEXSPI_GetInstance(base)]);

SDMA_StartTransfer(handle->txSdmaHandle);
/* Enable FLEXSPI TX SDMA. */
FLEXSPI_EnableTxDMA(base, true);
/* Start Transfer. */
base->IPCMD |= FLEXSPI_IPCMD_TRG_MASK;

Device config:

flexspi_device_config_t deviceconfig = {
.flexspiRootClk = 6250000,
.flashSize = FLASH_SIZE,
.CSIntervalUnit = kFLEXSPI_CsIntervalUnit1SckCycle,
.CSInterval = 2,
.CSHoldTime = 3,
.CSSetupTime = 3,
.dataValidTime = 0,
.columnspace = 0,
.enableWordAddress = 0,
.AWRSeqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE,
.AWRSeqNumber = 1,
.ARDSeqIndex = NOR_CMD_LUT_SEQ_IDX_READ_FAST,
.ARDSeqNumber = 1,
.AHBWriteWaitUnit = kFLEXSPI_AhbWriteWaitUnit2AhbCycle,
.AHBWriteWaitInterval = 0,
};

Page program command:

flashXfer.deviceAddress = dstAddr;
flashXfer.port = kFLEXSPI_PortA1;
flashXfer.cmdType = kFLEXSPI_Write;
flashXfer.SeqNumber = 1;
flashXfer.seqIndex = NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM_SINGLE;
flashXfer.data = (uint32_t *)src;
flashXfer.dataSize = FLASH_PAGE_SIZE;

DMA settings:

#define FLEXSPI_DMA (SDMAARM1)
#define FLEXSPI_TX_DMA_CHANNEL (1U)
#define FLEXSPI_RX_DMA_CHANNEL (2U)

SDMA_GetDefaultConfig(&sdmaConfig);
sdmaConfig.ratio = kSDMA_HalfARMClockFreq;
SDMA_Init(FLEXSPI_DMA, &sdmaConfig);
/* Create the SDMA channel handles */
SDMA_CreateHandle(&dmaTxHandle, FLEXSPI_DMA, FLEXSPI_TX_DMA_CHANNEL, &context_Tx);
SDMA_CreateHandle(&dmaRxHandle, FLEXSPI_DMA, FLEXSPI_RX_DMA_CHANNEL, &context_Rx);
dmaTxHandle.priority = 3;
dmaRxHandle.priority = 4;
SDMA_SetChannelPriority(FLEXSPI_DMA, FLEXSPI_TX_DMA_CHANNEL, 3U);
SDMA_SetChannelPriority(FLEXSPI_DMA, FLEXSPI_RX_DMA_CHANNEL, 4U);

LUT table the same as in the nor_flash example in RT family.

Also I see that FLEXSPI_TransferSDMACallback() works.

Could you help me with this issue?
Regards, Stanislav.

Re: QSPI IMX8MP CortexM7 DMA

Bio_TICFSL — Fri, 08 Sep 2023 19:31:41 GMT

Hello, I think you need to change the dtb,because The MX8MP Add flexspi DT node matching Linux kernel

"arm64: dts: imx8mp: Reorder flexspi clock-names entry"

Also I do not know if M7 core support SDMA.

Regards

Re: QSPI IMX8MP CortexM7 DMA

Stan88 — Fri, 08 Sep 2023 20:26:44 GMT

Hi @Bio_TICFSL

Thank you for the answer. But what about EDMA? Does it works on M7 and maybe there are some examples for it? Because in SDK there is only SDMA.

Regards.

Re: QSPI IMX8MP CortexM7 DMA

ceggers — Thu, 14 Sep 2023 07:11:57 GMT

Also I do not know if M7 core support SDMA.

I assume that using the SDMA is possible on the M7, but then you have to disable the SDMA on Cortex-A. I don't see the possibility to share the SDMA between both processors.

Some i.MX8 derivatives have more than one SDMA. But due to the limited routing of the SDMA events lines, I assume that assigning only the 2nd or 3rd SDMA instance to the M7 also matches only a few use cases.

regards,
Christian

Re: QSPI IMX8MP CortexM7 DMA

Stan88 — Wed, 20 Sep 2023 09:39:53 GMT

Hi Ceggers.

I don't run CortexA with Linux, I use only CortexM7 in my attemps. When I need to run Linux I disable SDMA it DTS files. So in my case it doesn't a root of problem.

Also I'm using SDMA1 because it has most possible use cases.

But it doesn't work. I see the first commands, but than no data. And also I can see the callback from SDMA that transfering was done. But again - no data, no clocks and CS is low.