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    <title>i.MX ProcessorsのトピックRe: IMXRT1064 SEMC - Read Operation Fail</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMXRT1064-SEMC-Read-Operation-Fail/m-p/1715623#M211863</link>
    <description>&lt;P&gt;Dear&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/196430"&gt;@Pavel_Hernandez&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Could you please help me if this breakdown is under your specialization?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks and Regards.&lt;/P&gt;</description>
    <pubDate>Fri, 01 Sep 2023 07:40:23 GMT</pubDate>
    <dc:creator>Lukas_Frank</dc:creator>
    <dc:date>2023-09-01T07:40:23Z</dc:date>
    <item>
      <title>IMXRT1064 SEMC - Read Operation Fail</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMXRT1064-SEMC-Read-Operation-Fail/m-p/1713289#M211665</link>
      <description>&lt;P&gt;Hi Dear Authorized,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I have been trying sequential read operations for months. My setups includes IMXRT1064 (Master) and FPGA (Slave) which is connected SEMC Interface. It stops after 1 read operation is occured. I examined SDK examples and below directions for configuration phase shared officially below:&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-RT-Knowledge-Base/How-to-configure-SRAM-in-SEMC-modules-for-RT-devices/ta-p/1559581" target="_blank"&gt;How to configure SRAM in SEMC modules for RT devic... - NXP Community&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Could you please help me about below questions?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Q1: The things I clearly face is; FPGA Logic Analyzer is address count is not increasing when I try to access SEMC_BASE address more than one. In the first initialization, IMXRT1064 request data from FPGA after the&amp;nbsp;&lt;SPAN&gt;SEMC_ConfigureSRAM function is executed, and then memory is fulfilling with FPGA datas. It is exactly happening when the base-&amp;gt;BR[6] = tempBRVal; line is executed. Why we are not able to request data from FPGA in sequential order when we access memory with below code portion?&lt;/SPAN&gt;&lt;/P&gt;&lt;LI-CODE lang="c"&gt;void SEMC_SRAMRead16Bit(void)
{
    uint32_t index = 0;

    uint16_t *sramFPGAData  = (uint16_t *)EXAMPLE_SEMC_START_ADDRESS;

    sram_readBuffer16B[index++] = sramFPGAData[index++];
    sram_readBuffer16B[index++] = sramFPGAData[index++];
    sram_readBuffer16B[index++] = sramFPGAData[index++];
    sram_readBuffer16B[index++] = sramFPGAData[index++];

    sram_readBuffer16B[index++] = sramFPGAData[index++];
    sram_readBuffer16B[index++] = sramFPGAData[index++];
    sram_readBuffer16B[index++] = sramFPGAData[index++];
    sram_readBuffer16B[index++] = sramFPGAData[index++];

    sram_readBuffer16B[index++] = sramFPGAData[index++];
    sram_readBuffer16B[index++] = sramFPGAData[index++];
    sram_readBuffer16B[index++] = sramFPGAData[index++];
    sram_readBuffer16B[index++] = sramFPGAData[index++];

    sram_readBuffer16B[index++] = sramFPGAData[index++];
    sram_readBuffer16B[index++] = sramFPGAData[index++];
    sram_readBuffer16B[index++] = sramFPGAData[index++];
    sram_readBuffer16B[index++] = sramFPGAData[index++];
}&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Q2: &lt;/STRONG&gt;Is there a specific register setting in IMXRT1064 for triggering the FPGA for read request?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I attached my whole source code. You can reference it for full acquisition of case.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks and Regards.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 29 Aug 2023 13:06:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMXRT1064-SEMC-Read-Operation-Fail/m-p/1713289#M211665</guid>
      <dc:creator>Lukas_Frank</dc:creator>
      <dc:date>2023-08-29T13:06:01Z</dc:date>
    </item>
    <item>
      <title>Re: IMXRT1064 SEMC - Read Operation Fail</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMXRT1064-SEMC-Read-Operation-Fail/m-p/1715623#M211863</link>
      <description>&lt;P&gt;Dear&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/196430"&gt;@Pavel_Hernandez&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Could you please help me if this breakdown is under your specialization?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thanks and Regards.&lt;/P&gt;</description>
      <pubDate>Fri, 01 Sep 2023 07:40:23 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMXRT1064-SEMC-Read-Operation-Fail/m-p/1715623#M211863</guid>
      <dc:creator>Lukas_Frank</dc:creator>
      <dc:date>2023-09-01T07:40:23Z</dc:date>
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