topic Re: iMXRT1176 - Slew rate and drive strength on SNVS pins in i.MX Processors

iMXRT1176 - Slew rate and drive strength on SNVS pins

stefano-quantic — Wed, 02 Aug 2023 13:15:34 GMT

The reference manual v2 (06/2023) says that SNVS pins do not have a slew rate option.
See section "12.4.2.21 SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW PAD Control Register (SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG)" and following.
Bit #0 is marked as "reserved" in this register.
For other pins, this bit is used for the slew rate setting SRE (e.g. see section "12.4.6.210 SW_PAD_CTL_PAD_GPIO_AD_00 SW PAD Control Register (SW_PAD_CTL_PAD_GPIO_AD_00)").

However, Config Tools let me select the slew rate for the SNVS pins too.

So, is the slew rate setting available on the SNVS pins?

Similarly for other pins whose registers are described in nearby sections:
SW_PAD_CTL_PAD_TEST_MODE_DIG
SW_PAD_CTL_PAD_POR_B_DIG
SW_PAD_CTL_PAD_ONOFF_DIG
SW_PAD_CTL_PAD_WAKEUP_DIG
SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG
SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG

The same for the adjacent bit DSE (#1), for the drive strength: it's marked as reserved in the reference manual, but Config Tools let me configure it.

Is it supported or not?

Re: iMXRT1176 - Slew rate and drive strength on SNVS pins

RaRo — Thu, 03 Aug 2023 21:43:09 GMT

Hello @stefano-quantic,

Let us double check if DSE and SRE are not being supported in SNVS, PMIC, POR, ONOFF and WAKEUP as i.MX RT1170 Processor Reference Manual mentions to give you a proper answer.

At the meantime, we are letting the team in charge to know about this.

Best regards, Raul.

Re: iMXRT1176 - Slew rate and drive strength on SNVS pins

RaRo — Wed, 30 Aug 2023 17:22:57 GMT

Hello @stefano-quantic,

First of all, we apologize for our delay.

Is it supported or not?

They are analog IO with limited function, and they do not support slew rate or drive strength configuration.

The tool is going to be updated. Thanks for the feedback.

Best regards, Raul.