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    <title>topic Re: [i.mx8mp] Boot from nand flash in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1712311#M211574</link>
    <description>&lt;P&gt;Hi,&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/202155"&gt;@Sanket_Parekh&lt;/a&gt;&amp;nbsp;.&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;NAND_CE1 was set to chip enable.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;After physically disconnecting the CS1 wire from the SoC to memory and booting up to U-Boot, I looked at the registers in the SoC and saw that the multiplexing was assigned to NAND_CE1.&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;But, NAND_CE1 has always been output low after power on.&lt;/P&gt;&lt;P&gt;Image attached.(D0:CE0 , D1:CE1, D2:RY/BY)&lt;/P&gt;&lt;P&gt;Therefore, I assume that CE0 and CE1 are active at the same time and cannot be boot.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Why NAND_CE1 output low?&lt;/P&gt;</description>
    <pubDate>Tue, 29 Aug 2023 04:28:41 GMT</pubDate>
    <dc:creator>junya</dc:creator>
    <dc:date>2023-08-29T04:28:41Z</dc:date>
    <item>
      <title>[i.mx8mp] Boot from nand flash</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1711869#M211517</link>
      <description>&lt;P&gt;&lt;SPAN&gt;I have a custom board with a i.MX8MP and a KIOKXIA TH58NVG4S0HTAK0 which should be used as boot device.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Boot device : NAND FLASH 2GB (2 chip select, 1chip select is 1GB)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;　&amp;nbsp; (Image size to be written is 1.6 GB)&lt;/P&gt;&lt;P&gt;brunch：imx-linux-hardknott&lt;/P&gt;&lt;P&gt;manifesto：imx-5.10.35 2.0.0.xml&lt;/P&gt;&lt;P&gt;DISTRO：fsl-imx-wayland&lt;/P&gt;&lt;P&gt;MACHINE：mx8mpevk&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;We tried to download yocto image with uuu tool but only 1GB of nand flash was recognized.&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;(Under these conditions, u-boot will boot up.)&lt;/P&gt;&lt;P&gt;This was due to the fact that CS1 was not multiplexed.&lt;/P&gt;&lt;P&gt;After modification, 2GB of nand flash is now recognized.&lt;/P&gt;&lt;P&gt;Next, we tried to boot, but it fails.&lt;BR /&gt;The following log was generated.&lt;/P&gt;&lt;P&gt;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~&lt;/P&gt;&lt;P&gt;U-Boot SPL 2021.04-5.10.35-2.0.0+g3463140881 (Jun 08 2021 - 01:39:44 +0000)&lt;BR /&gt;DDRINFO: start DRAM init&lt;BR /&gt;DDRINFO: DRAM rate 3200MTS&lt;BR /&gt;DDRINFO:ddrphy calibration done&lt;BR /&gt;DDRINFO: ddrmix config done&lt;BR /&gt;SEC0: RNG instantiated&lt;BR /&gt;Normal Boot&lt;BR /&gt;WDT: Not found!&lt;BR /&gt;Trying to boot from BOOTROM&lt;BR /&gt;image offset 0x100000, pagesize 0x1000, ivt offset 0x0&lt;BR /&gt;ROMAPI: download failure offset 0x158000 size 0x1000&lt;BR /&gt;SPL: failed to boot from all boot devices&lt;BR /&gt;### ERROR ### Please RESET the board ###&lt;/P&gt;&lt;P&gt;~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Is there anywhere else it should be fixed?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 28 Aug 2023 03:41:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1711869#M211517</guid>
      <dc:creator>junya</dc:creator>
      <dc:date>2023-08-28T03:41:37Z</dc:date>
    </item>
    <item>
      <title>Re: [i.mx8mp] Boot from nand flash</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1712279#M211566</link>
      <description>&lt;DIV&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/45153"&gt;@junya&lt;/a&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;I hope you are doing well.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Please make sure that the board include&amp;lt;.h&amp;gt; configuration contains the below configuration in uboot.&lt;/DIV&gt;
&lt;DIV&gt;(uboot-imx/include/configs/&lt;WBR /&gt;imx8mp_evk.h)&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;STRONG&gt;#define CONFIG_SYS_MAX_NAND_DEVICE&amp;nbsp; &amp;nbsp; &amp;nbsp;2&lt;BR /&gt;&lt;/STRONG&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Please also share other changes and configurations made for 2 CS in NAND for further debugging.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Thanks &amp;amp; Regards,&lt;/DIV&gt;
&lt;DIV&gt;Sanket Parekh&lt;/DIV&gt;</description>
      <pubDate>Mon, 28 Aug 2023 09:49:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1712279#M211566</guid>
      <dc:creator>Sanket_Parekh</dc:creator>
      <dc:date>2023-08-28T09:49:42Z</dc:date>
    </item>
    <item>
      <title>Re: [i.mx8mp] Boot from nand flash</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1712290#M211569</link>
      <description>&lt;P&gt;Hi,&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/202155"&gt;@Sanket_Parekh&lt;/a&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Thank you for your reply.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;＞#define CONFIG_SYS_MAX_NAND_DEVICE 2&lt;/P&gt;&lt;P&gt;Yes, this definition has been added.&lt;/P&gt;&lt;P&gt;No other modifications were made.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Perhaps NAND_CE1 is set to GPIO and is not functioning as chip enable.&lt;/P&gt;&lt;P&gt;Where do I change the pad setting?&lt;/P&gt;</description>
      <pubDate>Mon, 28 Aug 2023 10:04:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1712290#M211569</guid>
      <dc:creator>junya</dc:creator>
      <dc:date>2023-08-28T10:04:26Z</dc:date>
    </item>
    <item>
      <title>Re: [i.mx8mp] Boot from nand flash</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1712311#M211574</link>
      <description>&lt;P&gt;Hi,&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/202155"&gt;@Sanket_Parekh&lt;/a&gt;&amp;nbsp;.&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;NAND_CE1 was set to chip enable.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;After physically disconnecting the CS1 wire from the SoC to memory and booting up to U-Boot, I looked at the registers in the SoC and saw that the multiplexing was assigned to NAND_CE1.&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;But, NAND_CE1 has always been output low after power on.&lt;/P&gt;&lt;P&gt;Image attached.(D0:CE0 , D1:CE1, D2:RY/BY)&lt;/P&gt;&lt;P&gt;Therefore, I assume that CE0 and CE1 are active at the same time and cannot be boot.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Why NAND_CE1 output low?&lt;/P&gt;</description>
      <pubDate>Tue, 29 Aug 2023 04:28:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1712311#M211574</guid>
      <dc:creator>junya</dc:creator>
      <dc:date>2023-08-29T04:28:41Z</dc:date>
    </item>
    <item>
      <title>Re: [i.mx8mp] Boot from nand flash</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1713048#M211643</link>
      <description>&lt;P&gt;&lt;SPAN class="im"&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/45153"&gt;@junya&lt;/a&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;
&lt;DIV&gt;I hope you are doing well.&lt;/DIV&gt;
&lt;P&gt;&lt;LI-WRAPPER&gt;&lt;/LI-WRAPPER&gt;&lt;/P&gt;
&lt;DIV&gt;
&lt;P&gt;Can you please clarify after which change, U-boot fails to boot?&lt;/P&gt;
&lt;P&gt;One may also need to program nand fuse accordingly.&lt;/P&gt;
&lt;P&gt;Please refer to&amp;nbsp;&lt;STRONG&gt;6.1.5.4.1&amp;nbsp;&lt;/STRONG&gt;&lt;STRONG&gt;NAND eFUSE configuration&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;in&amp;nbsp;i.MX 8M Plus Applications Processor Reference Manual.&lt;/P&gt;
&lt;P&gt;Also refer to&amp;nbsp;&lt;STRONG&gt;NAND_CS_NUM [0x4B0] fuse in&amp;nbsp;Table 6-33. Boot Fusemap&lt;/STRONG&gt;&amp;nbsp;in&amp;nbsp;i.MX 8M Plus Applications Processor Reference Manual.&lt;/P&gt;
&lt;P&gt;Thanks &amp;amp; Regards,&lt;/P&gt;
&lt;P&gt;Sanket Parekh&lt;/P&gt;
&lt;/DIV&gt;</description>
      <pubDate>Tue, 29 Aug 2023 09:03:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1713048#M211643</guid>
      <dc:creator>Sanket_Parekh</dc:creator>
      <dc:date>2023-08-29T09:03:01Z</dc:date>
    </item>
    <item>
      <title>Re: [i.mx8mp] Boot from nand flash</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1713172#M211653</link>
      <description>&lt;P&gt;Hi,&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/202155"&gt;@Sanket_Parekh&lt;/a&gt;&amp;nbsp;.&lt;/P&gt;&lt;P&gt;Thank you for your helping.&lt;/P&gt;&lt;P&gt;It's not going well.&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P&gt;&lt;SPAN&gt;Can you please clarify after which change, U-boot fails to boot?&lt;/SPAN&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;SPAN&gt;The following is modified to nand boot.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp; - imx8mp-evk.dts&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; Add line 282, 343&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp; - imx8mp_evk.h&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; Modify line 242,&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; #define CONFIG_SYS_MAX_NAND_DEVICE 2&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; - nand_ids.c&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; Add line 57 ~59&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I am not sure why fuse boot is relevant.&lt;BR /&gt;Are you saying that internal boot does not support multiple nand devices?&lt;/P&gt;&lt;P&gt;When the boot mode is set to NAND boot and power is turned on, does the NAND_CE1 pad function as a GPIO? (output? input?)&lt;BR /&gt;Or does it function as NAND_CE1?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards.&lt;/P&gt;</description>
      <pubDate>Tue, 29 Aug 2023 10:30:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1713172#M211653</guid>
      <dc:creator>junya</dc:creator>
      <dc:date>2023-08-29T10:30:28Z</dc:date>
    </item>
    <item>
      <title>Re: [i.mx8mp] Boot from nand flash</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1714591#M211772</link>
      <description>&lt;P&gt;Hi,&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/202155"&gt;@Sanket_Parekh&lt;/a&gt;&amp;nbsp;.&lt;/P&gt;&lt;P&gt;In the nand boot, until the u-boot setting is reflected, NAND_CE1 seems to be a gpio setting. (input pin pull-down).&lt;BR /&gt;So by pulling up NAND_CE1 externally, I was able to successfully boot u-boot.&lt;BR /&gt;However, there is the next issue after that.&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Unable-to-access-multiple-nand-flash-on-u-boot/m-p/1714589#M211771" target="_blank"&gt;[i.mx8mp] Unable to access multiple nand flash on ... - NXP Community&lt;/A&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 31 Aug 2023 03:09:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1714591#M211772</guid>
      <dc:creator>junya</dc:creator>
      <dc:date>2023-08-31T03:09:22Z</dc:date>
    </item>
    <item>
      <title>Re: [i.mx8mp] Boot from nand flash</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1714696#M211777</link>
      <description>&lt;P&gt;&lt;SPAN class="im"&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/45153"&gt;@junya&lt;/a&gt;,&lt;/SPAN&gt;&lt;/P&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;I hope you are doing well.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;DIV&gt;It is required to pull up NAND_CE externally.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;From the dts, It seems that you have also enabled internal pull-up.&lt;/DIV&gt;
&lt;DIV&gt;MX8MP_IOMUXC_NAND_CE0_B__NAND_&lt;WBR /&gt;CE0_B 0x000001d6&lt;BR /&gt;MX8MP_IOMUXC_NAND_CE1_B__NAND_&lt;WBR /&gt;CE1_B 0x000001d6&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Please refer to&amp;nbsp;pinctrl_gpmi_nand node in&amp;nbsp;&lt;A href="https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts#L191" target="_blank" rel="noopener" data-saferedirecturl="https://www.google.com/url?q=https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/arch/arm64/boot/dts/freescale/imx8mp-ddr4-evk.dts%23L191&amp;amp;source=gmail&amp;amp;ust=1693548747860000&amp;amp;usg=AOvVaw3W4ei2J2AQa9-10Rng8FhJ"&gt;imx8mp-ddr4-evk.dts&lt;/A&gt;&amp;nbsp;for pad settings.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Please close this case.&lt;/DIV&gt;
&lt;DIV&gt;We will discuss this issue further on&amp;nbsp;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Unable-to-access-multiple-nand-flash-on-u-boot/m-p/1714589#M211771" target="_blank" rel="noopener" data-saferedirecturl="https://www.google.com/url?q=https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Unable-to-access-multiple-nand-flash-on-u-boot/m-p/1714589%23M211771&amp;amp;source=gmail&amp;amp;ust=1693548747860000&amp;amp;usg=AOvVaw3EeVeFPG21BbpHjmDJz8mi"&gt;[i.mx8mp] Unable to access multiple nand flash on ... - NXP Community&lt;/A&gt;&lt;/DIV&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Thanks &amp;amp; Regards,&lt;/DIV&gt;
&lt;P&gt;&lt;LI-WRAPPER&gt;&lt;/LI-WRAPPER&gt;Sanket Parekh&lt;/P&gt;</description>
      <pubDate>Thu, 31 Aug 2023 06:15:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1714696#M211777</guid>
      <dc:creator>Sanket_Parekh</dc:creator>
      <dc:date>2023-08-31T06:15:33Z</dc:date>
    </item>
    <item>
      <title>Re: [i.mx8mp] Boot from nand flash</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1714720#M211780</link>
      <description>&lt;DIV&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;The Advanced Boot Options screen lets you start Windows in advanced troubleshooting modes. You can access the menu by turning on your computer and pressing the&amp;nbsp;F8 key&amp;nbsp;before Windows&amp;nbsp;&lt;A href="https://lovelanguagetest.org/" target="_self"&gt;&amp;nbsp;&lt;/A&gt;&lt;SPAN&gt;&lt;A href="https://lovelanguagetest.org/" target="_self"&gt;love language test&amp;nbsp;&lt;/A&gt; &amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;&lt;SPAN class=""&gt;starts. Some options, such as safe mode, start Windows in a limited state, where only the bare essentials are started.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;SPAN&gt;UEFI boot mode refers to&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;the boot process used by UEFI firmware&lt;SPAN&gt;. UEFI stores all the information about initialization and startup in an . efi file that is saved on a special partition called EFI System Partition (ESP).&lt;/SPAN&gt;&lt;DIV&gt;&lt;DIV class=""&gt;&lt;DIV&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV class=""&gt;&lt;DIV&gt;&lt;DIV class=""&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Thu, 31 Aug 2023 06:50:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1714720#M211780</guid>
      <dc:creator>Larisabrownb</dc:creator>
      <dc:date>2023-08-31T06:50:59Z</dc:date>
    </item>
    <item>
      <title>Re: [i.mx8mp] Boot from nand flash</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1714721#M211781</link>
      <description>&lt;P&gt;Hi,&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/202155"&gt;@Sanket_Parekh&lt;/a&gt;&amp;nbsp;.&lt;/P&gt;&lt;P&gt;Thank you for your support.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P&gt;&lt;SPAN&gt;It is required to pull up NAND_CE externally.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;Yes,&amp;nbsp;Until the port setting is reflected in u-boot, it is a GPIO input setting, so an external pull-up is necessary.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P&gt;&lt;SPAN&gt;Please close this case.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;Please tell me one last thing.&lt;BR /&gt;Is it my understanding that I don't need to set up fuse. &lt;STRONG&gt;Is that correct?&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 31 Aug 2023 06:51:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1714721#M211781</guid>
      <dc:creator>junya</dc:creator>
      <dc:date>2023-08-31T06:51:05Z</dc:date>
    </item>
    <item>
      <title>Re: [i.mx8mp] Boot from nand flash</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1715543#M211845</link>
      <description>&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/45153"&gt;@junya&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I hope you are doing well.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Is it my understanding that I don't need to set up a fuse?&amp;nbsp;&lt;STRONG&gt;Is that correct?&lt;BR /&gt;&lt;/STRONG&gt;[Ans]: One needs to set up fuses, As it is the only way for ROM code to know about custom NAND flash.&lt;BR /&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;One needs to configure various parameters for custom NAND such as&amp;nbsp;NAND_CS_NUM,&amp;nbsp;NAND_GPMI_DDR_&lt;WBR /&gt;DLL_VAL ,&amp;nbsp;NAND_RST_TIME&amp;nbsp; NAND_READ_RETRY_SEQ_ID,&amp;nbsp;NAND_&lt;WBR /&gt;ROW_ADDR_BYTES, etc...&lt;/P&gt;
&lt;P&gt;Please refer to&amp;nbsp;&lt;STRONG&gt;6.1.5.4.1&amp;nbsp;&lt;/STRONG&gt;&lt;STRONG&gt;NAND eFUSE configuration&lt;/STRONG&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;and&amp;nbsp;&lt;STRONG&gt;Table 6-33. Boot Fusemap&lt;/STRONG&gt;&amp;nbsp;in&amp;nbsp;i.MX 8M Plus Applications Processor Reference Manual.&lt;/P&gt;
&lt;P&gt;One can also see&amp;nbsp;&lt;STRONG&gt;Boot Mode and CFG Switch sheet [page 21]&amp;nbsp;&lt;/STRONG&gt;in&amp;nbsp;&lt;STRONG&gt;&lt;A href="https://www.nxp.com/webapp/Download?colCode=8MPLUS-BB" target="_blank" rel="noopener" data-saferedirecturl="https://www.google.com/url?q=https://www.nxp.com/webapp/Download?colCode%3D8MPLUS-BB&amp;amp;source=gmail&amp;amp;ust=1693632649915000&amp;amp;usg=AOvVaw2kAb40mR71iWOIW4GnQMh6"&gt;i.MX 8M Plus EVK Base Board Design Files&lt;/A&gt;&lt;/STRONG&gt;&lt;/P&gt;
&lt;P&gt;&lt;EM&gt;Yes,&amp;nbsp;Until the port setting is reflected in u-boot, it is a GPIO input setting, so an external pull-up is necessary.&lt;BR /&gt;&lt;/EM&gt;=&amp;gt; NAND PAD will act as NAND functional pins and not as normal GPIO during ROM boot.&lt;/P&gt;
&lt;P&gt;Please make a note that at boot time only CS0 is supported.&lt;/P&gt;
&lt;P&gt;Please refer to&amp;nbsp;&lt;STRONG&gt;4.2 Boot device interface allocation&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/STRONG&gt;in&amp;nbsp;i.MX 8M Plus Applications Processor Datasheet.&lt;/P&gt;
&lt;P&gt;Have you tried removing the internal pull-up&amp;nbsp;from the pinctrl_gpmi_nand node in u-boot the device tree?&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Thanks &amp;amp; Regards,&lt;BR /&gt;Sanket Parekh&lt;/P&gt;</description>
      <pubDate>Fri, 01 Sep 2023 05:41:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1715543#M211845</guid>
      <dc:creator>Sanket_Parekh</dc:creator>
      <dc:date>2023-09-01T05:41:38Z</dc:date>
    </item>
    <item>
      <title>Re: [i.mx8mp] Boot from nand flash</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1715554#M211846</link>
      <description>&lt;BLOCKQUOTE&gt;&lt;P&gt;[Ans]: One needs to set up fuses, As it is the only way for ROM code to know about custom NAND flash.&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;What is the custom NAND flash ?&lt;/P&gt;&lt;P&gt;Do you mean multiple memory?&lt;/P&gt;&lt;P&gt;Is fuse setting always required for multiple memory?&lt;/P&gt;&lt;P&gt;(Sorry for all the questions.)&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P&gt;&lt;SPAN&gt;Please make a note that at boot time only CS0 is supported.&lt;/SPAN&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;Yes, so CS1 is not supported at boot time, I think it is a GPIO configuration.&lt;/P&gt;</description>
      <pubDate>Fri, 01 Sep 2023 06:01:05 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1715554#M211846</guid>
      <dc:creator>junya</dc:creator>
      <dc:date>2023-09-01T06:01:05Z</dc:date>
    </item>
    <item>
      <title>Re: [i.mx8mp] Boot from nand flash</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1716085#M211914</link>
      <description>&lt;P&gt;Hi, &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/202155"&gt;@Sanket_Parekh&lt;/a&gt;&amp;nbsp; san.&lt;/P&gt;&lt;P&gt;I have tried fuse-boot.&lt;/P&gt;&lt;P&gt;However, the phenomenon remained the same and the timing of access to CE1 was not correct.&lt;/P&gt;&lt;P&gt;I show fuse parameters under the below.&lt;/P&gt;&lt;P&gt;470h -&amp;gt; 10004140h&lt;/P&gt;&lt;P&gt;4A0h -&amp;gt; 00001E00h&lt;/P&gt;&lt;P&gt;4B0h -&amp;gt; 00000C79h&lt;/P&gt;&lt;P&gt;Other parameters remain at reset values.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards.&lt;/P&gt;</description>
      <pubDate>Mon, 04 Sep 2023 00:59:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1716085#M211914</guid>
      <dc:creator>junya</dc:creator>
      <dc:date>2023-09-04T00:59:58Z</dc:date>
    </item>
    <item>
      <title>Re: [i.mx8mp] Boot from nand flash</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1716394#M211956</link>
      <description>&lt;P&gt;&lt;SPAN class="im"&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/45153"&gt;@junya&lt;/a&gt;,&lt;/SPAN&gt;&lt;/P&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;I hope you are doing well.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;DIV&gt;Fuse settings seem correct, As the board boots properly till U-boot, This issue could not be due to the fuse,&lt;/DIV&gt;
&lt;DIV&gt;It could be due to a configuration issue in u-boot.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;We will discuss this query further in the&amp;nbsp;below post.&lt;/DIV&gt;
&lt;DIV&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Unable-to-access-multiple-nand-flash-on-u-boot/td-p/1714589" target="_blank" rel="noopener" data-saferedirecturl="https://www.google.com/url?q=https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Unable-to-access-multiple-nand-flash-on-u-boot/td-p/1714589&amp;amp;source=gmail&amp;amp;ust=1693902856154000&amp;amp;usg=AOvVaw1i0IhU1ZtaaA8osepeqgvI"&gt;https://community.nxp.com/t5/&lt;WBR /&gt;i-MX-Processors/i-mx8mp-&lt;WBR /&gt;Unable-to-access-multiple-&lt;WBR /&gt;nand-flash-on-u-boot/td-p/&lt;WBR /&gt;1714589&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV&gt;Hence, Please close this case to avoid duplicate replies.&lt;/DIV&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Thanks &amp;amp; Regards,&lt;/DIV&gt;
&lt;P&gt;&lt;LI-WRAPPER&gt;&lt;/LI-WRAPPER&gt;Sanket Parekh&lt;/P&gt;</description>
      <pubDate>Mon, 04 Sep 2023 09:09:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-mx8mp-Boot-from-nand-flash/m-p/1716394#M211956</guid>
      <dc:creator>Sanket_Parekh</dc:creator>
      <dc:date>2023-09-04T09:09:13Z</dc:date>
    </item>
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