topic Re: Why CPU DDR Memory Controller Has 2 Clock Outputs? in i.MX Processors

Why CPU DDR Memory Controller Has 2 Clock Outputs?

electronx — Sat, 12 Aug 2023 14:01:54 GMT

I'm trying to understand the ddr structure for the iMX6 Rex Module module. The cpu used is the MCIMX6Q5EYM10AC model from the nxp i.mx quad series.
www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf
www.imx6rex.com/wp-content/uploads/2016/04/iMX6-Rex-Module-Schematic.pdf
A configuration was made using 4 x16 DDR3 DRAM, with a total of 64 word lengths. So far everything is great. Why are there 2 (DRAM_SDCLK_0, DRAM_SDCLK_1 ) clock outputs?Does it matter from which clock source we feed the ddr chips?

Re: Why CPU DDR Memory Controller Has 2 Clock Outputs?

Harvey021 — Mon, 14 Aug 2023 09:06:20 GMT

Hi @electronx

In principle, these two clocks are the same, both come from a clock source (for example: PLL2 528M). Generally, clock1 is used for the first 32 bits, and clock0 is used for the last 32 bits.

Best regards

Harvey

Re: Why CPU DDR Memory Controller Has 2 Clock Outputs?

electronx — Mon, 14 Aug 2023 09:28:31 GMT

Thanks for your answer @Harvey021 . I also see that only the "SDCKE_0" pin is used for the clock enable status. Can the SDCKE_0 pin also control the DRAM_SDCLK_1 clock source?
Can SDCKE_1pin also check the ,clock source "DRAM_SDCLK_0" ?

Re: Why CPU DDR Memory Controller Has 2 Clock Outputs?

Harvey021 — Tue, 15 Aug 2023 08:49:51 GMT

SDCKE0 is only for clock0.

Best regards

Harvey

Re: Why CPU DDR Memory Controller Has 2 Clock Outputs?

electronx — Tue, 15 Aug 2023 10:04:06 GMT

SDCKE_1 pin is not connected anywhere. DRAM_SDCLK_1 clock source, how is it controlled?

Re: Why CPU DDR Memory Controller Has 2 Clock Outputs?

rudi_cyber — Tue, 15 Aug 2023 22:33:33 GMT

But the following is from NXP reference design iMX6Q-SABRE-SDB-DESIGNFILES.

As you said "SDCKE0 is only for clock0.", so NXP provides a wrong schematic for over 10 years, right?

So where we can download correct schematic? could you please provide link.

Re: Why CPU DDR Memory Controller Has 2 Clock Outputs?

Harvey021 — Fri, 18 Aug 2023 07:16:40 GMT

i.MX6Q support 64 bit data bus, and up to 2 ranks. So, it has 2 CS signals, 2 CKE signals, 2 ODT signals and 2 SDCLK. In theory, rank 0 should uses XXX_0, and rank 1 should uses xxx_1.

On NXP reference design, 6Q connects 4x DDR3 chips, each chip has 16 bit data bus. All 4 DDR3 chips are connected to rank 0, that is why they use xxx_0, but 2 of them connects to SDCK0 and the other 2 connects to SDCK1. Because SDCK0 and SDCK1 come from the same source, so they are equal. To facilitate PCB routing, if using T-topology, 2 connects to SDCK0 and 2 connects to SDCK1 is a good choice. All can be connected to SDCK0 if using Fly-by topology.

Best regards

Harvey

Re: Why CPU DDR Memory Controller Has 2 Clock Outputs?

rudi_cyber — Sat, 19 Aug 2023 01:14:45 GMT

In theory, rank 0 should uses XXX_0, and rank 1 should uses xxx_1.

Here is theory in i.MX6 reference manual.

We are talking about the DDR3 not the LPDDR2. Please note it.

We are talking about the T-TOP of the i.MX6 schemation design from NXP.

Ok, let's disscuss more further about fly-by. If we use fly-by and we mount ddr chip on the bottom layer.

According you input, connect to SDCK0, how to do layout? could it be tangle, there?

Still you did answer the quesion. You said "SDCKE0 is only for clock0."

Repeat the question.

The following is from NXP reference design iMX6Q-SABRE-SDB-DESIGNFILES.

As you said "SDCKE0 is only for clock0.", so NXP provides a wrong schematic for over 10 years, right?

So where we can download correct schematic? could you please provide link.