Distinguishing POR from POR-B assertion

eaad — Wed, 09 Aug 2023 10:17:10 GMT

Hi,

On the reference manual of i.MX RT1170 there is the following section

25.3.4 Reset behavior of the Power-on Reset
The Power-on Reset (POR) will assert when the chip is powered ON or the POR_B pin is
active. The POR will reset all of the chip except the Secure Non-Volatile Storage (SNVS)
block

As far as I understand, on the cases of POR, toggling the POR_B pin reset, the IPP_RESET_B occurs.

Therefore, by checking only this value after some reset I can't distinguish between those possible cases.

I would like to know if there is any exists option to distinguish between those case that maybe I missed during reading the manual.

Putting this in another words- after a reset I would like to know if the reset cause was from power or because someone actively (using some api he has) toggeled the POR_B reset pin. Can I do that without preserving other flags? Currently my planned solution is to put some magic on the SNVS (which is not battery backed, so should be initialized on POR), and then to check it on reset (that has the ipp_reset_b event). If it is initialized to zero, then I know the reset was caused by a POR, if it has the magic value I deduce that only the POR_B reset pin was toggeled.

I wonder if that's a best practice.

Thank you in advance for any comment,

Re: Distinguishing POR from POR-B assertion

EdwinHz — Wed, 09 Aug 2023 19:31:59 GMT

Hi @eaad,

I'm afraid ipp_reset_b is as far as the granularity of the POR detection goes. There is no discrete way of differentiating between power and pin resets for the POR.

That said, I believe your approach is a good workaround to differentiate between POR resets.

BR,
Edwin.

Re: Distinguishing POR from POR-B assertion

eaad — Thu, 10 Aug 2023 08:27:06 GMT

Thank you @EdwinHz

topic Re: Distinguishing POR from POR-B assertion in i.MX Processors

Distinguishing POR from POR-B assertion

Re: Distinguishing POR from POR-B assertion

Re: Distinguishing POR from POR-B assertion