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    <title>i.MX ProcessorsのトピックRe: reading adc multiple channel rt1064</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/reading-adc-multiple-channel-rt1064/m-p/1700474#M210417</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/216061"&gt;@sandeepc&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Please review de configuration of the SDK example&amp;nbsp;&lt;EM&gt;&lt;STRONG&gt;evkmimxrt1064_adc_12b1msps_sar_polling&lt;/STRONG&gt;&lt;/EM&gt;&lt;STRONG&gt;&amp;nbsp;&lt;/STRONG&gt;and replicate it to different channels.&lt;/P&gt;
&lt;P&gt;I don't understand why you have&amp;nbsp;&lt;SPAN&gt;&amp;nbsp;&lt;EM&gt;&lt;STRONG&gt;&amp;amp;BOARD_ADC1_channels_config[0]&lt;/STRONG&gt;&lt;/EM&gt; on&amp;nbsp;&lt;EM&gt;&lt;STRONG&gt;ADC_SetChannelConfig.&lt;/STRONG&gt;&lt;/EM&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Also you can use ConfigTools to do the configuration.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Best Regards, Miguel.&lt;/P&gt;</description>
    <pubDate>Mon, 07 Aug 2023 21:16:30 GMT</pubDate>
    <dc:creator>Miguel04</dc:creator>
    <dc:date>2023-08-07T21:16:30Z</dc:date>
    <item>
      <title>reading adc multiple channel rt1064</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/reading-adc-multiple-channel-rt1064/m-p/1697648#M210137</link>
      <description>&lt;P&gt;hi i need to read multiple adc channels from ADC1 by using software trigger by below configuration but i am able to read only adc i.e 1st input channel but i couldnt able to read second channel&amp;nbsp;&lt;/P&gt;&lt;P&gt;processor ==&amp;gt; imrt1064&lt;/P&gt;&lt;P&gt;adc pins i want to read ==&amp;gt;&lt;/P&gt;&lt;P&gt;GPIO_AD_B1_10&lt;BR /&gt;GPIO_AD_B1_11&lt;BR /&gt;GPIO_AD_B1_04&lt;BR /&gt;GPIO_AD_B1_05&lt;BR /&gt;GPIO_AD_B1_01&lt;BR /&gt;GPIO_AD_B1_00&lt;/P&gt;&lt;P&gt;MCUXpresso IDE v11.6.0 [Build 8187] [2022-07-13]&lt;/P&gt;&lt;P&gt;(c) Copyright 2006-2022 NXP&lt;/P&gt;&lt;DIV&gt;code=1&lt;/DIV&gt;&lt;DIV&gt;#include &amp;lt;stdio.h&amp;gt;&lt;/DIV&gt;&lt;DIV&gt;#include "board.h"&lt;/DIV&gt;&lt;DIV&gt;#include "peripherals.h"&lt;/DIV&gt;&lt;DIV&gt;#include "pin_mux.h"&lt;/DIV&gt;&lt;DIV&gt;#include "clock_config.h"&lt;/DIV&gt;&lt;DIV&gt;#include "MIMXRT1064.h"&lt;/DIV&gt;&lt;DIV&gt;#include "fsl_debug_console.h"&lt;/DIV&gt;&lt;DIV&gt;/* TODO: insert other include files here. */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;/* TODO: insert other definitions and declarations here. */&lt;/DIV&gt;&lt;DIV&gt;volatile uint32_t adch0,adch1;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;/*&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* @brief&amp;nbsp; &amp;nbsp;Application entry point.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*/&lt;/DIV&gt;&lt;DIV&gt;/* ADC1_IRQn interrupt handler */&lt;/DIV&gt;&lt;DIV&gt;void BOARD_ADC1_IRQHANDLER(void)&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;adch0 = ADC_GetChannelConversionValue(ADC1, 0);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;adch1 = ADC_GetChannelConversionValue(ADC1, 1);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ADC_SetChannelConfig(ADC1, 0, BOARD_ADC1_channels_config);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ADC_SetChannelConfig(ADC1, 1, BOARD_ADC1_channels_config);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;int main(void) {&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;/* Init board hardware. */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;BOARD_ConfigMPU();&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;BOARD_InitBootPins();&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;BOARD_InitBootClocks();&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;BOARD_InitBootPeripherals();&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;#ifndef BOARD_INIT_DEBUG_CONSOLE_PERIPHERAL&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;/* Init FSL debug console. */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;BOARD_InitDebugConsole();&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;#endif&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;PRINTF("Hello World\n");&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ADC_EnableHardwareTrigger(ADC1, 0);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ADC_SetChannelConfig(ADC1, 0, &amp;amp;BOARD_ADC1_channels_config[0]);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ADC_SetChannelConfig(ADC1, 1, &amp;amp;BOARD_ADC1_channels_config[1]);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;volatile static int i = 0 ;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;/* Enter an infinite loop, just incrementing a counter. */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;while(1) {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;i++ ;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;/* 'Dummy' NOP to allow source level single stepping of&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;tight while() loop */&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;__asm volatile ("nop");&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;return 0 ;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;P&gt;code 2&lt;/P&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;#include &amp;lt;stdio.h&amp;gt;&lt;/DIV&gt;&lt;DIV&gt;#include "board.h"&lt;/DIV&gt;&lt;DIV&gt;#include "peripherals.h"&lt;/DIV&gt;&lt;DIV&gt;#include "pin_mux.h"&lt;/DIV&gt;&lt;DIV&gt;#include "clock_config.h"&lt;/DIV&gt;&lt;DIV&gt;#include "MIMXRT1064.h"&lt;/DIV&gt;&lt;DIV&gt;#include "fsl_debug_console.h"&lt;/DIV&gt;&lt;DIV&gt;/* TODO: insert other include files here. */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;/* TODO: insert other definitions and declarations here. */&lt;/DIV&gt;&lt;DIV&gt;volatile uint32_t adch0,adch1;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;/*&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* @brief&amp;nbsp; &amp;nbsp;Application entry point.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*/&lt;/DIV&gt;&lt;DIV&gt;/* ADC1_IRQn interrupt handler */&lt;/DIV&gt;&lt;DIV&gt;void BOARD_ADC1_IRQHANDLER(void)&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;// while(1)&lt;/DIV&gt;&lt;DIV&gt;// {&lt;/DIV&gt;&lt;DIV&gt;// volatile static int a;&lt;/DIV&gt;&lt;DIV&gt;// a++;&lt;/DIV&gt;&lt;DIV&gt;// }&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;adch0 = ADC_GetChannelConversionValue(ADC1, 0);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;adch1 = ADC_GetChannelConversionValue(ADC1, 1);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ADC_SetChannelConfig(ADC1, 0, BOARD_ADC1_channels_config);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ADC_SetChannelConfig(ADC1, 1, BOARD_ADC1_channels_config);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;int main(void) {&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;/* Init board hardware. */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;BOARD_ConfigMPU();&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;BOARD_InitBootPins();&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;BOARD_InitBootClocks();&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;BOARD_InitBootPeripherals();&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;#ifndef BOARD_INIT_DEBUG_CONSOLE_PERIPHERAL&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;/* Init FSL debug console. */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;BOARD_InitDebugConsole();&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;#endif&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;PRINTF("Hello World\n");&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ADC_EnableHardwareTrigger(ADC1, 0);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ADC_SetChannelConfig(ADC1, 0, BOARD_ADC1_channels_config);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ADC_SetChannelConfig(ADC1, 1, BOARD_ADC1_channels_config);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;volatile static int i = 0 ;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;/* Enter an infinite loop, just incrementing a counter. */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;while(1) {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;i++ ;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;/* 'Dummy' NOP to allow source level single stepping of&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;tight while() loop */&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;__asm volatile ("nop");&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;return 0 ;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;whats wrong in my code help me out&lt;/P&gt;&lt;P&gt;regards&amp;nbsp;&lt;/P&gt;&lt;P&gt;Sandeep C&lt;/P&gt;&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/207690"&gt;@IMXRT1050&lt;/a&gt;&amp;nbsp;&lt;A href="https://community.nxp.com/t5/user/viewprofilepage/user-id/184336" target="_blank"&gt;@michael_imxrt&lt;/A&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;A href="https://community.nxp.com/t5/user/viewprofilepage/user-id/207690" target="_blank"&gt;@IMXRT1050&lt;/A&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;A href="https://community.nxp.com/t5/user/viewprofilepage/user-id/221012" target="_blank"&gt;@imxrt1062_PWM&lt;/A&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Wed, 02 Aug 2023 13:01:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/reading-adc-multiple-channel-rt1064/m-p/1697648#M210137</guid>
      <dc:creator>sandeepc</dc:creator>
      <dc:date>2023-08-02T13:01:55Z</dc:date>
    </item>
    <item>
      <title>Re: reading adc multiple channel rt1064</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/reading-adc-multiple-channel-rt1064/m-p/1698408#M210201</link>
      <description>&lt;P&gt;&lt;SPAN&gt;The channel groups are used in a "ping-pong" approach to control the ADC operation. At any point, only one of the channel groups is actively controlling ADC conversions. The&lt;STRONG&gt; channel group 0&lt;/STRONG&gt; is used for&lt;STRONG&gt; both software and hardware trigger modes&lt;/STRONG&gt;. Channel&lt;STRONG&gt; groups 1 and greater&lt;/STRONG&gt; indicate potentially&lt;STRONG&gt; multiple channel group&lt;/STRONG&gt; registers for&lt;STRONG&gt; use only&lt;/STRONG&gt; in&lt;STRONG&gt; hardware trigger mode.&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&lt;STRONG&gt;None of the channel groups 1 or greater are used for software trigger operation&lt;/STRONG&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;In software trigger mode as i referred to understand&amp;nbsp; how api actually works i gone through this&amp;nbsp; it says like above&amp;nbsp;&lt;A href="https://mcuxpresso.nxp.com/api_doc/dev/721/group__adc__12b1msps__sar.html#ga2036da14750059b15c079e2c1d783c64" target="_blank"&gt;https://mcuxpresso.nxp.com/api_doc/dev/721/group__adc__12b1msps__sar.html#ga2036da14750059b15c079e2c1d783c64&lt;/A&gt;&lt;/P&gt;&lt;P&gt;but in software trigger if i want read&amp;nbsp; the multiple channels how can i retrieve the multiple channels adc results because if configure like below&amp;nbsp;&lt;/P&gt;&lt;P&gt;ADC_SetChannelConfig(ADC1, 0, &amp;amp;BOARD_ADC1_channels_config[0]); ==&amp;gt;IN 6 ADC1&lt;BR /&gt;ADC_SetChannelConfig(ADC1, 0, &amp;amp;BOARD_ADC1_channels_config[1]); ==&amp;gt;IN 5 ADC1&lt;/P&gt;&lt;P&gt;data will place in to the base-&amp;gt; r register if i want to read IN 5 ADC1 how can i read because both IN 6 and IN5 has channel group 0 it point to same indexes please can you justify how to difretiate it&lt;/P&gt;&lt;P&gt;i tried like below also&lt;/P&gt;&lt;DIV&gt;/*&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* Copyright 2016-2023 NXP&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* All rights reserved.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* Redistribution and use in source and binary forms, with or without modification,&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* are permitted provided that the following conditions are met:&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* o Redistributions of source code must retain the above copyright notice, this list&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*&amp;nbsp; &amp;nbsp;of conditions and the following disclaimer.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* o Redistributions in binary form must reproduce the above copyright notice, this&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*&amp;nbsp; &amp;nbsp;list of conditions and the following disclaimer in the documentation and/or&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*&amp;nbsp; &amp;nbsp;other materials provided with the distribution.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* o Neither the name of NXP Semiconductor, Inc. nor the names of its&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*&amp;nbsp; &amp;nbsp;contributors may be used to endorse or promote products derived from this&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*&amp;nbsp; &amp;nbsp;software without specific prior written permission.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*/&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;/**&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* @file&amp;nbsp; &amp;nbsp; adc_2_1.c&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* @brief&amp;nbsp; &amp;nbsp;Application entry point.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*/&lt;/DIV&gt;&lt;DIV&gt;#include &amp;lt;stdio.h&amp;gt;&lt;/DIV&gt;&lt;DIV&gt;#include "board.h"&lt;/DIV&gt;&lt;DIV&gt;#include "peripherals.h"&lt;/DIV&gt;&lt;DIV&gt;#include "pin_mux.h"&lt;/DIV&gt;&lt;DIV&gt;#include "clock_config.h"&lt;/DIV&gt;&lt;DIV&gt;#include "MIMXRT1064.h"&lt;/DIV&gt;&lt;DIV&gt;#include "fsl_debug_console.h"&lt;/DIV&gt;&lt;DIV&gt;/* TODO: insert other include files here. */&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;/* TODO: insert other definitions and declarations here. */&lt;/DIV&gt;&lt;DIV&gt;volatile uint32_t g_AdcConversionValue[2],g_AdcConversionValue1;&lt;/DIV&gt;&lt;DIV&gt;static int i=0;&lt;/DIV&gt;&lt;DIV&gt;/*&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;* @brief&amp;nbsp; &amp;nbsp;Application entry point.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;*/&lt;/DIV&gt;&lt;DIV&gt;/* ADC1_IRQn interrupt handler */&lt;/DIV&gt;&lt;DIV&gt;void BOARD_ADC1_IRQHANDLER(void)&lt;/DIV&gt;&lt;DIV&gt;{&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;g_AdcConversionValue[i++] = ADC_GetChannelConversionValue(ADC1, 0);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ADC_SetChannelConfig(ADC1, 0, &amp;amp;BOARD_ADC1_channels_config[i]);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;if(i == 2)&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;i=0;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;int main(void) {&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;/* Init board hardware. */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;BOARD_ConfigMPU();&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;BOARD_InitBootPins();&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;BOARD_InitBootClocks();&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;BOARD_InitBootPeripherals();&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;#ifndef BOARD_INIT_DEBUG_CONSOLE_PERIPHERAL&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;/* Init FSL debug console. */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;BOARD_InitDebugConsole();&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;#endif&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;PRINTF("Hello World\n");&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;ADC_SetChannelConfig(ADC1, 0, &amp;amp;BOARD_ADC1_channels_config[0]);&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;/* Force the counter to be placed into memory. */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;volatile static int i = 0 ;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;/* Enter an infinite loop, just incrementing a counter. */&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;while(1) {&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;i++ ;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;/* 'Dummy' NOP to allow source level single stepping of&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; tight while() loop */&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;__asm volatile ("nop");&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;}&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;&lt;SPAN&gt;return 0 ;&lt;/SPAN&gt;&lt;/DIV&gt;&lt;DIV&gt;}&lt;/DIV&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;static inline uint32_t ADC_GetChannelConversionValue(ADC_Type *base, uint32_t channelGroup)&lt;BR /&gt;{&lt;BR /&gt;assert(channelGroup &amp;lt; (uint32_t)FSL_FEATURE_ADC_CONVERSION_CONTROL_COUNT);&lt;/P&gt;&lt;P&gt;return base-&amp;gt;R[channelGroup];&lt;BR /&gt;}&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/9237"&gt;@miguel&lt;/a&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Thu, 03 Aug 2023 07:56:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/reading-adc-multiple-channel-rt1064/m-p/1698408#M210201</guid>
      <dc:creator>sandeepc</dc:creator>
      <dc:date>2023-08-03T07:56:06Z</dc:date>
    </item>
    <item>
      <title>Re: reading adc multiple channel rt1064</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/reading-adc-multiple-channel-rt1064/m-p/1700474#M210417</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/216061"&gt;@sandeepc&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Please review de configuration of the SDK example&amp;nbsp;&lt;EM&gt;&lt;STRONG&gt;evkmimxrt1064_adc_12b1msps_sar_polling&lt;/STRONG&gt;&lt;/EM&gt;&lt;STRONG&gt;&amp;nbsp;&lt;/STRONG&gt;and replicate it to different channels.&lt;/P&gt;
&lt;P&gt;I don't understand why you have&amp;nbsp;&lt;SPAN&gt;&amp;nbsp;&lt;EM&gt;&lt;STRONG&gt;&amp;amp;BOARD_ADC1_channels_config[0]&lt;/STRONG&gt;&lt;/EM&gt; on&amp;nbsp;&lt;EM&gt;&lt;STRONG&gt;ADC_SetChannelConfig.&lt;/STRONG&gt;&lt;/EM&gt;&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Also you can use ConfigTools to do the configuration.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Best Regards, Miguel.&lt;/P&gt;</description>
      <pubDate>Mon, 07 Aug 2023 21:16:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/reading-adc-multiple-channel-rt1064/m-p/1700474#M210417</guid>
      <dc:creator>Miguel04</dc:creator>
      <dc:date>2023-08-07T21:16:30Z</dc:date>
    </item>
    <item>
      <title>Re: reading adc multiple channel rt1064</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/reading-adc-multiple-channel-rt1064/m-p/1700659#M210428</link>
      <description>&lt;P&gt;ok let me try in polling method, but our application we are preferring for interrupt is there any method for aquring more than 2channels in interrupt method.&lt;/P&gt;&lt;P&gt;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/206759"&gt;@Miguel04&lt;/a&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 08 Aug 2023 03:37:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/reading-adc-multiple-channel-rt1064/m-p/1700659#M210428</guid>
      <dc:creator>sandeepc</dc:creator>
      <dc:date>2023-08-08T03:37:55Z</dc:date>
    </item>
    <item>
      <title>Re: reading adc multiple channel rt1064</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/reading-adc-multiple-channel-rt1064/m-p/1701249#M210472</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/216061"&gt;@sandeepc&lt;/a&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;On the SDK files you can find the adc interrupt example too.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Best Regards, Miguel.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 08 Aug 2023 16:52:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/reading-adc-multiple-channel-rt1064/m-p/1701249#M210472</guid>
      <dc:creator>Miguel04</dc:creator>
      <dc:date>2023-08-08T16:52:15Z</dc:date>
    </item>
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