RMII PHY on i.MX8MP with external reference clock

benpicco — Thu, 03 Aug 2023 14:44:47 GMT

Hello,

we are connecting a KSZ8091RNA PHY to the i.MX8MP processor found on the phyCORE-i.MX8MP module using the RMII interface.

The PHY is generating the reference clock, but when I configure the i.MX8MP to not generate the reference clock by adding snps,rmii_refclk_ext to the eqos device tree node, the MAC does not receive the input clock:

[ 5.052963] imx-dwmac 30bf0000.ethernet eth1: PHY [stmmac-1:00] driver [Micrel KSZ8081 or KSZ8091] (irq=POLL) [ 6.069309] imx-dwmac 30bf0000.ethernet: Failed to reset the dma [ 6.075355] imx-dwmac 30bf0000.ethernet eth1: stmmac_hw_setup: DMA engine initialization failed [ 6.084129] imx-dwmac 30bf0000.ethernet eth1: stmmac_open: Hw setup failed

When I remove the snps,rmii_refclk_ext option the interface comes up, but it looks like the PHY and the MAC both generate the reference clock on separate pins and can't exchange Ethernet data:

[ 2.247814] imx-dwmac 30bf0000.ethernet: User ID: 0x10, Synopsys ID: 0x51 [ 2.254640] imx-dwmac 30bf0000.ethernet: DWMAC4/5 [ 2.259453] imx-dwmac 30bf0000.ethernet: DMA HW capability register supported [ 2.266597] imx-dwmac 30bf0000.ethernet: RX Checksum Offload Engine supported [ 2.273740] imx-dwmac 30bf0000.ethernet: TX Checksum insertion supported [ 2.280449] imx-dwmac 30bf0000.ethernet: Wake-Up On Lan supported [ 2.286603] imx-dwmac 30bf0000.ethernet: Enable RX Mitigation via HW Watchdog Timer [ 2.294270] imx-dwmac 30bf0000.ethernet: Enabled Flow TC (entries=8) [ 2.300638] imx-dwmac 30bf0000.ethernet: Enabling HW TC (entries=256, max_off=256) [ 2.308214] imx-dwmac 30bf0000.ethernet: Using 34 bits DMA width [ 5.242914] imx-dwmac 30bf0000.ethernet eth1: PHY [stmmac-1:00] driver [Micrel KSZ8081 or KSZ8091] (irq=POLL) [ 5.259271] imx-dwmac 30bf0000.ethernet eth1: No Safety Features support found [ 5.266580] imx-dwmac 30bf0000.ethernet eth1: IEEE 1588-2008 Advanced Timestamp supported [ 5.277944] imx-dwmac 30bf0000.ethernet eth1: registered PTP clock [ 5.292434] imx-dwmac 30bf0000.ethernet eth1: configuring for phy/rmii link mode [ 8.382960] imx-dwmac 30bf0000.ethernet eth1: Link is Up - 100Mbps/Full - flow control rx/tx

But no data is received and when I send something, I don't see any packets in Wireshark on a 2nd machine connected via Ethernet

eth1 Link encap:Ethernet HWaddr 50:2D:F4:24:67:4A inet6 addr: fe80::522d:f4ff:fe24:674a/64 Scope:Link UP BROADCAST MULTICAST MTU:1500 Metric:1 RX packets:0 errors:0 dropped:0 overruns:0 frame:0 TX packets:738 errors:0 dropped:0 overruns:0 carrier:0 collisions:0 txqueuelen:1000 RX bytes:0 (0.0 B) TX bytes:118312 (115.5 KiB) Interrupt:44

My 'working' device tree is

&eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; phy-mode = "rmii"; phy-handle = <&ethphy1>; status = "okay"; // snps,rmii_refclk_ext; mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; ethphy1: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; }; }; }; &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; pinctrl_eqos: eqosgrp { fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x90 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x4000001f >; }; };

tbh I have no idea how those pinctrl values are determined - I just copied them from other boards and they don't match the IOMUXC registers from the data sheet - so what are they?

I understand that MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK must be the crucial value here, but how do I configure it as input?

Thank you for your help!

Re: RMII PHY on i.MX8MP with external reference clock

Dhruvit — Mon, 07 Aug 2023 06:54:37 GMT

Hi @benpicco,

Q) but it looks like the PHY and the MAC both generate the reference clock on separate pins and can't exchange Ethernet data:

=> Here, The device tree seems correct. Please share your schematics for further debugging the issue.

Q) I have no idea how those pinctrl values are determined

=>The pinctrl values should be configured as per the pad control registers from the reference manual.

i,e. For ENET_MDIO, the properties like slew rate, pull up, open drain, etc.. can be configured according to section 8.2.4.170 SW_PAD_CTL_PAD_ENET_MDIO SW PAD Control Register from the reference manual IMX8MPRM.

Thanks & Regards,

Dhruvit Vasavada

Re: RMII PHY on i.MX8MP with external reference clock

benpicco — Mon, 07 Aug 2023 10:22:49 GMT

Thank you for confirming that the configuration should behave as expected - it turned out to be a hardware issue: CRS_DV / RXCTL and REF_CLK were not connected correctly. (We had it on TXCK instead of TD2)

With the PHY wired up properly things are working fine now.

Re: RMII PHY on i.MX8MP with external reference clock

Dhruvit — Mon, 07 Aug 2023 12:43:34 GMT

Hi @benpicco,

I hope you are doing well

Glad to know that query has been resolved. If there is no further query should I mark this thread as closed?

Thanks & Regards,

Dhruvit Vasavada

topic Re: RMII PHY on i.MX8MP with external reference clock in i.MX Processors

RMII PHY on i.MX8MP with external reference clock

Re: RMII PHY on i.MX8MP with external reference clock

Re: RMII PHY on i.MX8MP with external reference clock

Re: RMII PHY on i.MX8MP with external reference clock