topic Re: i.MX8MP EQOS RMII DMA issue in i.MX Processors

i.MX8MP EQOS RMII DMA issue

domzippi — Tue, 31 May 2022 10:28:43 GMT

I'm trying to configure the EQOS MAC for RMII connection with a TJA1102 phy on my custom i.MX8MP board. The PHY initialization looks correct, however, I always get the following error:

[ 7.823171] imx-dwmac 30bf0000.ethernet: Failed to reset the dma [ 7.829205] imx-dwmac 30bf0000.ethernet eth1: stmmac_hw_setup: DMA engine initialization failed [ 7.838562] imx-dwmac 30bf0000.ethernet eth1: stmmac_open: Hw setup failed

My device tree looks like this:

eqos: ethernet@30bf0000 { compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a"; reg = <0x30bf0000 0x10000>; interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "eth_wake_irq", "macirq"; clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>, <&clk IMX8MP_CLK_QOS_ENET_ROOT>, <&clk IMX8MP_CLK_ENET_QOS_TIMER>, <&clk IMX8MP_CLK_ENET_QOS>; clock-names = "stmmaceth", "pclk", "ptp_ref", "tx"; assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>, <&clk IMX8MP_CLK_ENET_QOS_TIMER>, <&clk IMX8MP_CLK_ENET_QOS>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, <&clk IMX8MP_SYS_PLL2_100M>, <&clk IMX8MP_SYS_PLL2_50M>; assigned-clock-rates = <0>, <100000000>, <50000000>; // -> reconfigured to 50 MHz for RMII nvmem-cells = <&eth_mac2>; nvmem-cell-names = "mac-address"; nvmem_macaddr_swap; intf_mode = <&gpr 0x4>; status = "disabled"; }; };

&eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; phy-mode = "rmii"; phy-handle = <&ethphy1>; /delete-property/ phy-supply; status = "okay"; max-speed = <100>; mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; ethphy1: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; }; }; };

pinctrl_eqos: eqosgrp { fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 MX8MP_IOMUXC_ENET_RD2__GPIO1_IO28 0x91 MX8MP_IOMUXC_ENET_RD3__GPIO1_IO29 0x91 MX8MP_IOMUXC_ENET_RXC__ENET_QOS_RX_ER 0x91 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x12 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x12 MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x12 MX8MP_IOMUXC_ENET_TD3__GPIO1_IO18 0x1f MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x12 MX8MP_IOMUXC_ENET_TXC__ENET_QOS_TX_ER 0x12 >; };

I can see the 50 MHz clock output on the TD2 pad, but the rest of the RMII interface is doing nothing.

What am I missing?

In the reference manual I found the following remark:

Does this mean that there is anything else to do except setting the GPR_ENET_QOS_INTF_SEL field to RMII (which is done by dwmac-imx.c)?

Re: i.MX8MP EQOS RMII DMA issue

domzippi — Wed, 01 Jun 2022 13:02:00 GMT

I was able to resolve the issue by letting the PHY create the RMII ref clock. After adapting the dts (adding "snps,rmii_refclk_ext"), the DMA reset worked and I'm able to use the network interface as expected.

The only change is this bit in the IOMUX_GPR_GPR1 register:

Can someone please clarify why creating the clock directly (IMX8MP_SYS_PLL2_50M) does not work, but using an external clock works without a problem? When measured, both clocks looked valid (50 MHz).

Re: i.MX8MP EQOS RMII DMA issue

benpicco — Wed, 02 Aug 2023 15:30:20 GMT

Hi, I'm facing the same issue as you are - how did you solve it?

I tried adding snps,rmii_refclk_ext to the eqos node of the device tree and otherwise copied your device tree (I'm also using i.MX8MP but with a KSZ8091 PHY) but to no avail - I still see the Failed to reset the dma message while I do see the clock being active on the scope.

Did you further modify the device tree from your initial question? Thank you a lot!

Re: i.MX8MP EQOS RMII DMA issue

domzippi — Thu, 03 Aug 2023 14:12:36 GMT

Hi,

No I don't have any other changes in my device tree...

My working eqos node looks like this:

/* ethernet on baseboard */ &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; phy-mode = "rmii"; phy-handle = <&ethphy1>; status = "okay"; max-speed = <100>; /* FIXME: this seems to be necessary for RMII */ snps,rmii_refclk_ext; mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; ethphy1: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0x0>; /*tja110x,refclk_in;*/ }; }; };

Have you adjusted the PLL config in arch/arm64/boot/dts/freescale/imx8mp.dtsi for the 50 MHz clock? Other than that it worked fine on my board, once the PHY was providing the 50 MHz reference clock...

Re: i.MX8MP EQOS RMII DMA issue

benpicco — Thu, 03 Aug 2023 14:25:01 GMT

I tried that

--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -1219,8 +1219,8 @@ eqos: ethernet@30bf0000 { <&clk IMX8MP_CLK_ENET_QOS>; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, <&clk IMX8MP_SYS_PLL2_100M>, - <&clk IMX8MP_SYS_PLL2_125M>; - assigned-clock-rates = <0>, <100000000>, <125000000>; + <&clk IMX8MP_SYS_PLL2_50M>; + assigned-clock-rates = <0>, <100000000>, <50000000>; nvmem-cells = <&eth_mac2>; nvmem-cell-names = "mac-address"; nvmem_macaddr_swap;

but to no avail.

I'm now using your pinmux settings (just copied the pinctrl_eqos node) - how did you arrive at the value for MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK?

Re: i.MX8MP EQOS RMII DMA issue

domzippi — Fri, 04 Aug 2023 07:42:29 GMT

how did you arrive at the value for MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK?

The hex values are settings for the pinmux pad (pull up, slew rate, etc.). You can find them in the reference manual, or by using the i.MX pinmux config tool. TBH, I don't know how I determined the value... It might not be completly correct, because this pin is used as an input now... But in my setup it works...

You said you can see the 50 MHz clock from the PHY on this pin (TD2)? Is the clock already there when the kernel initializes the MAC?

Re: i.MX8MP EQOS RMII DMA issue

benpicco — Fri, 04 Aug 2023 11:25:17 GMT

Ah thank you, so the hex values don't select the functionality but just influence the analog characteristics of the pin?

Yes I see the 50 MHz already before Linux boots, when I enable the snps,rmii_refclk_ext option I see the clock disappear as soon as the MAC gets initialized - but I guess that's just Linux disabling the PHY when it can't bring up the interface?

Re: i.MX8MP EQOS RMII DMA issue

domzippi — Fri, 04 Aug 2023 11:41:23 GMT

Yes, the functionality of the pinmux is selected by the macro name.

I don't know how your PHY works, but this sounds a little bit strange to me... Is your PHY detected correctly? Do you need any additional PHY settings? Maybe your PHY driver disables / reconfigures the clock output during kernel boot and thats why it disappeares and why the MAC can't see it?

Re: i.MX8MP EQOS RMII DMA issue

benpicco — Fri, 04 Aug 2023 14:47:08 GMT

Turns out there was also a hardware issue, now that the PHY is wired up correctly it works as expected

I didn't even need the changes to imx8mp.dtsi in the end.

Re: i.MX8MP EQOS RMII DMA issue

Jens-Stieglitz — Tue, 24 Oct 2023 14:24:32 GMT

Hi all!

I managed to make iMX8MP generating RMII clock and working. SION bit for TD2 has to be on. This is done by proper pinmux configuration. According to pinctrl/fsl,imx-pinctrl.txt to enable SION one should set bit 30 in the pad config. Here is my dtb config:

&eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos_rmii>; phy-mode = "rmii"; phy-handle = <&ethphy0>; snps,force_thresh_dma_mode; snps,mtl-tx-config = <&mtl_tx_setup>; snps,mtl-rx-config = <&mtl_rx_setup>; status = "okay"; assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>, <&clk IMX8MP_SYS_PLL2_100M>, <&clk IMX8MP_SYS_PLL2_50M>; assigned-clock-rates = <0>, <100000000>, <50000000>; mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>; #size-cells = <0>; ethphy0: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; }; };

And pinmux config:

pinctrl_eqos_rmii: eqosgrp { fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 MX8MP_IOMUXC_ENET_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK 0x40000016 // RMII.REF_CLK MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 // RMII.TX_EN MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 // RMII.CRS_DV MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 >; };

I did not change dtsi. One can configure clock by overriding values in dts file.

Re: i.MX8MP EQOS RMII DMA issue

yangx — Tue, 11 Jun 2024 06:32:32 GMT

The pinctrl is good！ thanks！