topic Re: FlexSPI DQS STR / SDR query in i.MX Processors

FlexSPI DQS STR / SDR query

DanielNis — Wed, 26 Jul 2023 12:25:54 GMT

According to: https://www.nxp.com/docs/en/data-sheet/IMXRT1160XEC.pdf,
When defining the FlexSPIn_MCR0[RXCLKSRC] = 0x3,
the FlexSPI controller samples read data on a half delayes DQS falling edge.

According to JEDEC SFDP for STR / SDR the flash NOR with DQS/DS (data strobe) can work mode (10b):
first rising edge of DS in the middle of the first data bit, start of second data bit aligned with the first falling edge of DS, first rising edge of DS follows a Rising edge of CK.(CLK/SCK)

Please advised how FlexSPI can also support DQS STR/SDR flash NOR with mode 10b, as described above, as current implementation cause the read to skip first DQS/DS/RWDS clock signal.

Thank you and regards,
Daniel.N

Re: FlexSPI DQS STR / SDR query

jingpan — Fri, 28 Jul 2023 08:27:54 GMT

Hi @DanielNis ,

But it seems no problem. There is only a short delay after the clock edge. What is your flash?

Regards,

Jing

Re: FlexSPI DQS STR / SDR query

DanielNis — Wed, 02 Aug 2023 06:46:20 GMT

Hi Jing,

Please see the following picture to clearify the issue:

Thanks,
Daniel.N

Re: FlexSPI DQS STR / SDR query

jingpan — Wed, 02 Aug 2023 09:39:49 GMT

Hi @DanielNis ,

I think RT's datasheet doesn't make it clear. Because actually we don't see such problem.

Regards,

Jing