topic Re: i.MX8MM watchdog SRS function clarification in i.MX Processors

i.MX8MM watchdog SRS function clarification

andersmo — Thu, 20 Jul 2023 10:04:50 GMT

The documentation of the SRS bit in the WDOGx_WCR register for the i.MX8M Mini states:

Software Reset Signal. Controls the software assertion of the WDOG-generated reset signal
WDOG_RESET_B_DEB. This bit automatically resets to 1 after it has been asserted to 0. For proper operation of this function, the SRE bit in this register must be set to 1.

Is the sentence about the SRE bit accurate? In the documentation for e.g. the i.MX7, the description of the SRS bit doesn't mention SRE, and the description of the SRE bit says that it's for "an option(sic) way to generate software reset". This "more robust" software reset doesn't seem to be documented anywhere, but I digress...

In both U-Boot and the Linux kernel, the software reset implementation only asserts the SRS bit, not SRE, yet both are able to reboot properly. Am I misunderstanding something?

Re: i.MX8MM watchdog SRS function clarification

JorgeCas — Thu, 20 Jul 2023 22:13:02 GMT

Hello, I hope you are doing well.

Researching about the statement "more robust software reset" I found that whatever SRE is 0 or 1, SRS =0 to all can do the software reset.

The difference of SRE between 1 and 0, is from the reset behavior, when SRE is 1, it keeps reset until system reset completed, while SRE is 0, it just trigger reset without waiting for reset status.

But, since on i.MX8MM reference manual states that SRE must be set to 1 and 0 is reserved so, we cannot warranty the correct behavior with SRE = 0.

Best regards.

Re: i.MX8MM watchdog SRS function clarification

andersmo — Fri, 21 Jul 2023 09:17:24 GMT

Thanks for the explanation.