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    <title>i.MX Processorsのトピックi.MX 8M Plus LPDDR4 single rank memory problem</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Plus-LPDDR4-single-rank-memory-problem/m-p/1679282#M208398</link>
    <description>&lt;P&gt;I am working with a custom PCB which has a MIMX8ML8CVNKZAB CPU and a&amp;nbsp;MT53E1G32D2FW LPDDR4 memory from Micron. DDR calibration was completed successfully and sequential memory test works fine. However pseudo random data pattern test doesn't work.&amp;nbsp;&lt;/P&gt;&lt;P&gt;The LPDDR4 is a 4GB dual channel single rank memory and looks like that recommend memories for these processors are all dual rank. Has anyone worked with this kind of CPU memory combination and could confirm if it is possible to get this running. It looks like that atleast in DDR tools it is not possible to define single rank memory&lt;/P&gt;&lt;P&gt;BR, Timo&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Fri, 30 Jun 2023 06:06:01 GMT</pubDate>
    <dc:creator>TimoV</dc:creator>
    <dc:date>2023-06-30T06:06:01Z</dc:date>
    <item>
      <title>i.MX 8M Plus LPDDR4 single rank memory problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Plus-LPDDR4-single-rank-memory-problem/m-p/1679282#M208398</link>
      <description>&lt;P&gt;I am working with a custom PCB which has a MIMX8ML8CVNKZAB CPU and a&amp;nbsp;MT53E1G32D2FW LPDDR4 memory from Micron. DDR calibration was completed successfully and sequential memory test works fine. However pseudo random data pattern test doesn't work.&amp;nbsp;&lt;/P&gt;&lt;P&gt;The LPDDR4 is a 4GB dual channel single rank memory and looks like that recommend memories for these processors are all dual rank. Has anyone worked with this kind of CPU memory combination and could confirm if it is possible to get this running. It looks like that atleast in DDR tools it is not possible to define single rank memory&lt;/P&gt;&lt;P&gt;BR, Timo&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 30 Jun 2023 06:06:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Plus-LPDDR4-single-rank-memory-problem/m-p/1679282#M208398</guid>
      <dc:creator>TimoV</dc:creator>
      <dc:date>2023-06-30T06:06:01Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX 8M Plus LPDDR4 single rank memory problem</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Plus-LPDDR4-single-rank-memory-problem/m-p/1679418#M208412</link>
      <description>&lt;P&gt;pls refer to the link&lt;/P&gt;
&lt;P&gt;"&lt;A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Quad-8M-Mini-8M-Nano-8M-Plus-maximum-supported-LPDDR4/ta-p/1434761&amp;quot;" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Quad-8M-Mini-8M-Nano-8M-Plus-maximum-supported-LPDDR4/ta-p/1434761"&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="joanxie_0-1688113446536.png" style="width: 400px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/230262i830573B827CA3FC7/image-size/medium?v=v2&amp;amp;px=400" role="button" title="joanxie_0-1688113446536.png" alt="joanxie_0-1688113446536.png" /&gt;&lt;/span&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;FONT size="2"&gt;Byte-mode LPDDR4 devices (x16 channel internally split between two dies, x8 each) of any density are not supported therefore, the numbers are applicable only to devices with x16 internal organization (referred to as "standard" in the JEDEC specification).&lt;/FONT&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 30 Jun 2023 08:30:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX-8M-Plus-LPDDR4-single-rank-memory-problem/m-p/1679418#M208412</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2023-06-30T08:30:07Z</dc:date>
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