FlexCAN RX FIFO filter not accepting

cpham2 — Thu, 29 Jun 2023 23:48:53 GMT

Evaluation board: MIMXRT1170-EVK

Spec: i.MX RT1170 Processor Reference Manual (document number: IMXRT1170RM Rev. 1, 05/2021)

I am facing an issue with RX FIFO CAN filter. I only care about extended ID bits 24 down to 21 to be zero. I configure ID filter table elements 0 to 7 located at addresses: E0, E4, E8, EC, F0, F4, F8, FC to 0x4000_0000 and RXFGMASK to 0x01E0_0000. I send a test CAN message with ID 0x001F8001(bits 24:21 = 0). I don’t get a match. However, if I change the RXFGMASK to 0x0, then I get a match. It does not matter if I set the other RXMGMASK, RX14MASK, RX15MASK and RXIMR[63:0] to 0x0 or 0xffff_ffff. According to the reference manual, section 66.3.8 Rx FIFO (page 5310), if MCR[IRMQ] = 0, then the FIFO filter is affected by RXFGMASK. Below is the setup of the CAN configuration. I wonder if I miss any bit setup. Greatly appreciate your help. Thanks.

Regards,

Chau

CAN controller configurations: MCR, CTRL2, ID filter table and mask registers.

MCR 0x20a2000f RW 0x40c3c000 Module Configuration register

…

MCR[REFEN] = 1(enable RX fifo receive) bit 29th

MCR[IRMQ] = 0 (individual RX masking disable) bit 16

MCR[IDAM] = 0 (format A) bit(9:8)

MCR[MAXMB] = 0xf (16 MB configuration) bit(6:0)

…

CTRL2 0x00b10000 RW 0x40c3c034 Control 2 register

…

CTRL2[RFFN] = 0 (8 RX FIFO filter element)

CTRL2[MRP] = 0 (matching starts from RX FIFO and continues on mailboxes

…

According to the reference manual, section 66.3.8 Rx FIFO, if MCR[IRMQ] = 0, then the FIFO filter is affected by RXFGMASK. Any

RXMGMASK 0x00000000 RW 0x40c3c010 Rx Mailboxes Global Mask register

RX14MASK 0x00000000 RW 0x40c3c014 Rx 14 Mask register

RX15MASK 0x00000000 RW 0x40c3c018 Rx 15 Mask register

RXFGMASK 0x01e00000 RW 0x40c3c048 Rx FIFO Global Mask register

RXIMR[63:0] 0x00000000 RW 0x40c3c880 Rx Individual Mask registers

ID filter table: E0, E4, E8, EC, F0, F4, F8 and FC are configured to 0x4000_0000.

CS6 0x40000000 RW 0x40c3c0e0 Message Buffer 6 CS Register

MB1_64B_WORD4_L 0x40000000 RW 0x40c3c0e0 Message Buffer 1 WORD_64B Register

MB2_32B_WORD2_L 0x40000000 RW 0x40c3c0e0 Message Buffer 2 WORD_32B Register

MB4_16B_CS_L 0x40000000 RW 0x40c3c0e0 Message Buffer 4 CS Register

MB6_8B_CS 0x40000000 RW 0x40c3c0e0 Message Buffer 6 CS Register

ID6 0x40000000 RW 0x40c3c0e4 Message Buffer 6 ID Register

MB1_64B_WORD5_L 0x40000000 RW 0x40c3c0e4 Message Buffer 1 WORD_64B Register

MB2_32B_WORD3_L 0x40000000 RW 0x40c3c0e4 Message Buffer 2 WORD_32B Register

MB4_16B_ID_L 0x40000000 RW 0x40c3c0e4 Message Buffer 4 ID Register

MB6_8B_ID 0x40000000 RW 0x40c3c0e4 Message Buffer 6 ID Register

MB1_64B_WORD6_L 0x40000000 RW 0x40c3c0e8 Message Buffer 1 WORD_64B Register

MB2_32B_WORD4_L 0x40000000 RW 0x40c3c0e8 Message Buffer 2 WORD_32B Register

MB4_16B_WORD0_L 0x40000000 RW 0x40c3c0e8 Message Buffer 4 WORD_16B Register

MB6_8B_WORD0 0x40000000 RW 0x40c3c0e8 Message Buffer 6 WORD_8B Register

WORD06 0x40000000 RW 0x40c3c0e8 Message Buffer 6 WORD0 Register

MB1_64B_WORD7_L 0x40000000 RW 0x40c3c0ec Message Buffer 1 WORD_64B Register

MB2_32B_WORD5_L 0x40000000 RW 0x40c3c0ec Message Buffer 2 WORD_32B Register

MB4_16B_WORD1_L 0x40000000 RW 0x40c3c0ec Message Buffer 4 WORD_16B Register

MB6_8B_WORD1 0x40000000 RW 0x40c3c0ec Message Buffer 6 WORD_8B Register

WORD16 0x40000000 RW 0x40c3c0ec Message Buffer 6 WORD1 Register

CS7 0x40000000 RW 0x40c3c0f0 Message Buffer 7 CS Register

MB1_64B_WORD8_L 0x40000000 RW 0x40c3c0f0 Message Buffer 1 WORD_64B Register

MB2_32B_WORD6_L 0x40000000 RW 0x40c3c0f0 Message Buffer 2 WORD_32B Register

MB4_16B_WORD2_L 0x40000000 RW 0x40c3c0f0 Message Buffer 4 WORD_16B Register

MB7_8B_CS 0x40000000 RW 0x40c3c0f0 Message Buffer 7 CS Register

ID7 0x40000000 RW 0x40c3c0f4 Message Buffer 7 ID Register

MB1_64B_WORD9_L 0x40000000 RW 0x40c3c0f4 Message Buffer 1 WORD_64B Register

MB2_32B_WORD7_L 0x40000000 RW 0x40c3c0f4 Message Buffer 2 WORD_32B Register

MB4_16B_WORD3_L 0x40000000 RW 0x40c3c0f4 Message Buffer 4 WORD_16B Register

MB7_8B_ID 0x40000000 RW 0x40c3c0f4 Message Buffer 7 ID Register

MB1_64B_WORD10_L 0x40000000 RW 0x40c3c0f8 Message Buffer 1 WORD_64B Register

MB3_32B_CS_L 0x40000000 RW 0x40c3c0f8 Message Buffer 3 CS Register

MB5_16B_CS_L 0x40000000 RW 0x40c3c0f8 Message Buffer 5 CS Register

MB7_8B_WORD0 0x40000000 RW 0x40c3c0f8 Message Buffer 7 WORD_8B Register

WORD07 0x40000000 RW 0x40c3c0f8 Message Buffer 7 WORD0 Register

MB1_64B_WORD11_L 0x40000000 RW 0x40c3c0fc Message Buffer 1 WORD_64B Register

MB3_32B_ID_L 0x40000000 RW 0x40c3c0fc Message Buffer 3 ID Register

MB5_16B_ID_L 0x40000000 RW 0x40c3c0fc Message Buffer 5 ID Register

MB7_8B_WORD1 0x40000000 RW 0x40c3c0fc Message Buffer 7 WORD_8B Register

WORD17 0x40000000 RW 0x40c3c0fc Message Buffer 7 WORD1 Register

Re: FlexCAN RX FIFO filter not accepting

Omar_Anguiano — Tue, 11 Jul 2023 00:18:14 GMT

Hello
I hope you are well.

I'm checking your configuration to check if something is missing or if a field is not set correctly.

Best regards,
Omar

topic FlexCAN RX FIFO filter not accepting in i.MX Processors

FlexCAN RX FIFO filter not accepting

Re: FlexCAN RX FIFO filter not accepting