IMX8MN RMII to ADIN1200 Phy

EHecht — Thu, 15 Jun 2023 09:13:50 GMT

Hello

We are currently trying to bring up our ethernet phy on our custom board using a digi imx8mn nano som and an Analog Devices ADIN1200 using the MDIO and RMII interface. The imx8mn shall provide the 50MHz clk_ref for the rmii interface to the phy and its internal MAC as described in the IMX reference manual Table 11-42 and ADIN datasheet page 12 table 14. When powering up the board the phy is not found with the following message:

root@ccimx8mn-cc-a:~# dmesg | grep eth
[ 2.098277] mdio_bus 30be0000.ethernet-1: MDIO device at address 0 is missing.
[ 2.106146] fec 30be0000.ethernet eth0: registered PHC device 0
[ 5.796575] fec 30be0000.ethernet eth0: Unable to connect to phy

However we can see a clock signal on the mdc line and some activity on the mdio line. We can not observe a clock signal on the ETH_REF_CLK line. If we give the phy id manually in the device tree with `compatible = "ethernet-phy-id0282.bc20", "ethernet-phy-ieee802.3-c22";` an eth0 shows up but is not operational. Using mii-diag tool it reports no valid mii device.

The device tree and the relevant parts of the schematic are shown below.

Schematic

```` device tree

&fec1 {
    pinctrl-names = "default";
    pinctrl-0 = <&pinctrl_fec1_gpio>,
        <&pinctrl_fec1>;
    phy-mode = "rmii";
    phy-handle = <&ethphy0>;

/* Set the proper voltage regulator. */

    // assigned-clock-rates = <0>, <100000000>, <125000000>, <50000000>;
    phy-reset-gpios = <&gpio4 27 GPIO_ACTIVE_LOW>;
    phy-reset-duration = <1>;
    fsl,magic-packet;

    status = "okay";
    mdio {
   #address-cells = <1>;
   #size-cells = <0>;

   ethphy0: ethernet-phy@0 {
       /*
        * cc-a board is equipted with the ADIN12000 phy
        * see https://www.digi.com/resources/documentation/digidocs/embedded/dey/4.0/cc8mnano/bsp-   ethernet_r_8m
        * and https://wiki.analog.com/resources/tools-software/linux-drivers/net-phy/adin
        */
        // compatible = "adi,adin";
        // compatible = "ethernet-phy-id0282.bc20", "ethernet-phy-ieee802.3-c22";
        compatible = "ethernet-phy-ieee802.3-c22";
        reg = <0>;
        adi,fifo-depth-bits = <8>;
        status = "okay";
        interrupt-parent = <&gpio3>;
        interrupts = <25 IRQ_TYPE_EDGE_FALLING>;

};
};
};

&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;

pinctrl_fec1: fec1grp {
    fsl,pins = <
    MX8MN_IOMUXC_ENET_MDC_ENET1_MDC 0x3
    MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23
    MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
    MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
    MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
    MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
    MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
    MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
    MX8MN_IOMUXC_ENET_RXC_ENET1_RX_ER 0x91
    MX8MN_IOMUXC_ENET_TD2_ENET1_TX_CLK 0x4000001f
    >;
};

pinctrl_fec1_gpio: fec1gpiogrp {
    fsl,pins = <
    /* PHY reset */
    MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x16
    /* PHY interrupt */
    MX8MN_IOMUXC_SAI5_MCLK_GPIO3_IO25 0x41
    >;
};

};

````

Re: IMX8MN RMII to ADIN1200 Phy

Sanket_Parekh — Mon, 19 Jun 2023 09:23:22 GMT

Hi @EHecht

I hope you are doing well.

Please make sure that the correct compatible string is used with PHY ID.

Please make sure that the GPR_ENET1_TX_CLK_SEL bit in the IOMUXC_GPR_GPR1 register is set.

Please look at 8.2.3.2 General Purpose Register 1 (IOMUXC_GPR_GPR1) in i.MX 8M Nano Applications Processor Reference Manual.

One can refer to the below-mentioned code in u-boot.

/board/freescale/imx8mn_evk/imx8mn_evk.c

Please share full boot logs for further debugging.

Thanks & Regards,

Sanket Parekh

topic IMX8MN RMII to ADIN1200 Phy in i.MX Processors

IMX8MN RMII to ADIN1200 Phy

Re: IMX8MN RMII to ADIN1200 Phy