<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックMIMX8ML8DVNLZAB</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/MIMX8ML8DVNLZAB/m-p/1661817#M206941</link>
    <description>&lt;P&gt;&lt;SPAN&gt;Hello NXP team,&amp;nbsp;&lt;BR /&gt;We are designing a hardware platform using &lt;/SPAN&gt;&lt;STRONG&gt;&lt;U&gt;MIMX8ML8DVNLZAB&lt;/U&gt;&lt;/STRONG&gt;&lt;SPAN&gt; processor.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;We required a qualified LPDDR and eMMC list of&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;&lt;U&gt;MIMX8ML8DVNLZAB.&lt;/U&gt;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Please help us to get the details&amp;nbsp;asap.&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Thu, 01 Jun 2023 10:44:43 GMT</pubDate>
    <dc:creator>JyotiVaishnav</dc:creator>
    <dc:date>2023-06-01T10:44:43Z</dc:date>
    <item>
      <title>MIMX8ML8DVNLZAB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MIMX8ML8DVNLZAB/m-p/1661817#M206941</link>
      <description>&lt;P&gt;&lt;SPAN&gt;Hello NXP team,&amp;nbsp;&lt;BR /&gt;We are designing a hardware platform using &lt;/SPAN&gt;&lt;STRONG&gt;&lt;U&gt;MIMX8ML8DVNLZAB&lt;/U&gt;&lt;/STRONG&gt;&lt;SPAN&gt; processor.&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;We required a qualified LPDDR and eMMC list of&amp;nbsp;&lt;/SPAN&gt;&lt;STRONG&gt;&lt;U&gt;MIMX8ML8DVNLZAB.&lt;/U&gt;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Please help us to get the details&amp;nbsp;asap.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 01 Jun 2023 10:44:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MIMX8ML8DVNLZAB/m-p/1661817#M206941</guid>
      <dc:creator>JyotiVaishnav</dc:creator>
      <dc:date>2023-06-01T10:44:43Z</dc:date>
    </item>
    <item>
      <title>Re: MIMX8ML8DVNLZAB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/MIMX8ML8DVNLZAB/m-p/1662642#M207011</link>
      <description>&lt;P&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/218187"&gt;@JyotiVaishnav&lt;/a&gt;&amp;nbsp;,&lt;/P&gt;
&lt;P&gt;I hope you are doing well.&lt;/P&gt;
&lt;P&gt;Regarding eMMC, i.MX8MP processor supports&amp;nbsp;MMC standard, up to version 5.1. It supports&amp;nbsp;1-bit/4-bit/8-bit MMC mode. Any eMMC meeting this requirement can be used with i.MX8MP processor.&lt;/P&gt;
&lt;P&gt;Regarding DRAM, one can refer to the below link which mentions the list of validated memories.&lt;BR /&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Quad-8M-Mini-8M-Nano-8M-Plus-maximum-supported-LPDDR4/ta-p/1434761" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/i-MX-8M-Quad-8M-Mini-8M-Nano-8M-Plus-maximum-supported-LPDDR4/ta-p/1434761&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;One can also refer to the i.MX8MP EVK's schematic to take the reference of qualified part numbers of eMMC and DRAM.&lt;/P&gt;
&lt;P&gt;&lt;A href="https://www.nxp.com/webapp/Download?colCode=8MPLUSLPD4-CPU" target="_self"&gt;i.MX 8M Plus LPDDR4 EVK Compute Module Design Files&amp;nbsp;&lt;/A&gt;&lt;/P&gt;
&lt;P&gt;Thanks &amp;amp; Regards,&lt;BR /&gt;Ritesh M Patel&lt;/P&gt;</description>
      <pubDate>Fri, 02 Jun 2023 11:18:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/MIMX8ML8DVNLZAB/m-p/1662642#M207011</guid>
      <dc:creator>riteshmpatel</dc:creator>
      <dc:date>2023-06-02T11:18:09Z</dc:date>
    </item>
  </channel>
</rss>

