Leakage problem

sapirbuz — Thu, 08 Jun 2023 08:11:27 GMT

Hi,

We have a leakage problem: our GPIOs are powered before the MCU power banks (see pictures below); the +v3.3_main rail has 2V leakage and as a result, the MCU can't wake up. the SNVS needs to power up before the other rail.

The GPIO pins are powered all the time and we can't change that.

I tried to force the +v3.3_main rail to be 0V, but it changed the GPIOs and affected our design.

since you know better the internal NXP MCU architecture, can you please offer a solution to isolate the +V3.3V_main rail from the GPIOs and solve the leakage problem?

I have attached the design schematics

picture 1, the signals that are powered first: ( connected to 3.3V pull-ups rails that are always up):

picture 2, Are powered after:

Re: Leakage problem

Hui_Ma — Thu, 01 Jun 2023 01:01:22 GMT

Hi,

In general, we don't recommend to discuss customer board hardware design at this public community. We would suggest customer to use our confidential support channel to submit a ticket.

Please refer below picture to submit an online technical support ticket, then our engineer will handle/answer that ticket. Thank you for the understanding.

best regards,

Mike

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Leakage problem

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