https://community.nxp.com/t5/i-MX-Processors/Implementing-software-for-Cypress-S71-Combo-Multi-Chip/m-p/1658478#M206653 <P>Hi,</P><P>I'm currently working on the flexspi interface between an I.mx RT1052 and a hyperbus combo device (Infineon S71 - 1,8V - 512Mb HyperFLASH, 64Mb HyperRAM). The board was originally equipped with a hyperFLASH, but was modified to accept a combo chip.</P><P>Unfortunately, I can't figure out how to make the chip function correctly. I can access and boot from the hyperflash, but was wondering how to Read/Write in the HyperRAM.</P><P>What are the setup steps for the combo chips? Which files do I have to alter to switch from a simple hyperFLASH chip to the combo?</P><P>Also, is there an application note somewhere concerning implementation of the MCPs?</P><P>Thanks in advance</P> Fri, 26 May 2023 14:29:44 GMT dsonderer 2023-05-26T14:29:44Z https://community.nxp.com/t5/i-MX-Processors/Implementing-software-for-Cypress-S71-Combo-Multi-Chip/m-p/1658478#M206653 <P>Hi,</P><P>I'm currently working on the flexspi interface between an I.mx RT1052 and a hyperbus combo device (Infineon S71 - 1,8V - 512Mb HyperFLASH, 64Mb HyperRAM). The board was originally equipped with a hyperFLASH, but was modified to accept a combo chip.</P><P>Unfortunately, I can't figure out how to make the chip function correctly. I can access and boot from the hyperflash, but was wondering how to Read/Write in the HyperRAM.</P><P>What are the setup steps for the combo chips? Which files do I have to alter to switch from a simple hyperFLASH chip to the combo?</P><P>Also, is there an application note somewhere concerning implementation of the MCPs?</P><P>Thanks in advance</P> Fri, 26 May 2023 14:29:44 GMT https://community.nxp.com/t5/i-MX-Processors/Implementing-software-for-Cypress-S71-Combo-Multi-Chip/m-p/1658478#M206653 dsonderer 2023-05-26T14:29:44Z https://community.nxp.com/t5/i-MX-Processors/Implementing-software-for-Cypress-S71-Combo-Multi-Chip/m-p/1659287#M206751 <P>Hello<BR />I hope you are well.</P> <P>From my understanding, the device connected to RT1050 is an IC that contains HyperFlash and HyperRAM correct?<BR />If both memories are connected to the same FlexSPI interface then there are issues when you access both devices at the same time.<BR />To avoid this, I suggest you execute the code in the internal RAM so the XIP in Flash does not collide with HyperRAM.</P> <P>These application notes might be helpful: <BR /><A href="https://www.nxp.com/docs/en/nxp/application-notes/AN12239.pdf" target="_blank">How to Enable HyperRAM with i.MX RT (nxp.com)</A><BR /><A href="https://www.nxp.com/docs/en/application-note/AN13028.pdf" target="_blank">Advanced HyperRAM/PSRAM Usage on i.MX RT (nxp.com)</A></P> <P>Best regards,<BR />Omar</P> Mon, 29 May 2023 19:20:08 GMT https://community.nxp.com/t5/i-MX-Processors/Implementing-software-for-Cypress-S71-Combo-Multi-Chip/m-p/1659287#M206751 Omar_Anguiano 2023-05-29T19:20:08Z