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    <title>topic i.MX8M-Plus U-Boot RDC settings in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-U-Boot-RDC-settings/m-p/1658206#M206618</link>
    <description>&lt;P&gt;In the "&lt;SPAN&gt;i.MX 8M Plus Applications Processor Reference Manual, Rev. 1, 06/2021" I read the chapter "3.2 Resource Domain Controller (RDC)" and I see the reset value for the several RDC_PDAPxxx registers.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;On my evaluation board, if I halt the boot inside U-Boot, I see that 3 RDC_PDAPxxx registers have values different from the reset/default value:&lt;/SPAN&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;RDC_PDAP8 which is SAI3 has a value of 0x00000003&lt;/LI&gt;&lt;LI&gt;RDC_PDAP29 which is RDC has a value of 0x0000000B&lt;/LI&gt;&lt;LI&gt;RDC_PDAP105 which is UART2 has a value of 0x00000003&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;SPAN&gt;Can someone explain where in the U-Boot sources (&lt;A href="https://github.com/nxp-imx/uboot-imx" target="_self"&gt;https://github.com/nxp-imx/uboot-imx&lt;/A&gt;) I can see the section responsible for these settings.&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;And, moreover, why they're necessary.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;In my usage scenario I would like using UART2 from Cortex-M (domain 1), but it doesn't seem possible without patching the default U-Boot from NXP.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;But I prefer not to going on with these, because I see it as a difficult job, with possible heavy consequences in case of mistakes.&lt;/SPAN&gt;&lt;/P&gt;</description>
    <pubDate>Fri, 26 May 2023 08:14:48 GMT</pubDate>
    <dc:creator>vix</dc:creator>
    <dc:date>2023-05-26T08:14:48Z</dc:date>
    <item>
      <title>i.MX8M-Plus U-Boot RDC settings</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-U-Boot-RDC-settings/m-p/1658206#M206618</link>
      <description>&lt;P&gt;In the "&lt;SPAN&gt;i.MX 8M Plus Applications Processor Reference Manual, Rev. 1, 06/2021" I read the chapter "3.2 Resource Domain Controller (RDC)" and I see the reset value for the several RDC_PDAPxxx registers.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;On my evaluation board, if I halt the boot inside U-Boot, I see that 3 RDC_PDAPxxx registers have values different from the reset/default value:&lt;/SPAN&gt;&lt;/P&gt;&lt;UL&gt;&lt;LI&gt;RDC_PDAP8 which is SAI3 has a value of 0x00000003&lt;/LI&gt;&lt;LI&gt;RDC_PDAP29 which is RDC has a value of 0x0000000B&lt;/LI&gt;&lt;LI&gt;RDC_PDAP105 which is UART2 has a value of 0x00000003&lt;/LI&gt;&lt;/UL&gt;&lt;P&gt;&lt;SPAN&gt;Can someone explain where in the U-Boot sources (&lt;A href="https://github.com/nxp-imx/uboot-imx" target="_self"&gt;https://github.com/nxp-imx/uboot-imx&lt;/A&gt;) I can see the section responsible for these settings.&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;And, moreover, why they're necessary.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;In my usage scenario I would like using UART2 from Cortex-M (domain 1), but it doesn't seem possible without patching the default U-Boot from NXP.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;But I prefer not to going on with these, because I see it as a difficult job, with possible heavy consequences in case of mistakes.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 26 May 2023 08:14:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-U-Boot-RDC-settings/m-p/1658206#M206618</guid>
      <dc:creator>vix</dc:creator>
      <dc:date>2023-05-26T08:14:48Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8M-Plus U-Boot RDC settings</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-U-Boot-RDC-settings/m-p/1658382#M206639</link>
      <description>&lt;DIV&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/149059"&gt;@vix&lt;/a&gt;&amp;nbsp;,&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;I hope you are doing well.&lt;BR /&gt;&lt;BR /&gt;&lt;/DIV&gt;
&lt;DIV&gt;RDC PDAP registers are configured in ATF.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Please refer to&amp;nbsp;imx_rdc_cfg in&amp;nbsp;&lt;A href="https://github.com/nxp-imx/imx-atf/blob/lf_v2.6/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c" target="_blank" rel="noopener" data-saferedirecturl="https://www.google.com/url?q=https://github.com/nxp-imx/imx-atf/blob/lf_v2.6/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c&amp;amp;source=gmail&amp;amp;ust=1685187544670000&amp;amp;usg=AOvVaw13ZcCcAZEZIjYrHCCnJ3Ew"&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;imx-atf/plat/imx/imx8m/imx8mp/&lt;WBR /&gt;imx8mp_bl31_setup.c&amp;nbsp;&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;One can add the below line in imx_rdc_cfg in imx8mp_bl31_setup.c to use UART2 in the m7 core.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&lt;STRONG&gt;RDC_PDAPn(RDC_PDAP_UART2, D1R | D1W),&lt;BR /&gt;&lt;/STRONG&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;STRONG&gt;&amp;nbsp;&lt;/STRONG&gt;&lt;/DIV&gt;
&lt;DIV&gt;Please make sure to add the below node in the dts file.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;uart2{&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;status = "disabled";&lt;/DIV&gt;
&lt;DIV&gt;}&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Please make a note that uart2 is used for debug console in default BSP.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;One needs to make changes to use another uart as A53 debug console.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Thanks &amp;amp; Regards,&lt;/DIV&gt;
&lt;DIV&gt;Sanket Parekh&lt;/DIV&gt;</description>
      <pubDate>Fri, 26 May 2023 11:40:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-U-Boot-RDC-settings/m-p/1658382#M206639</guid>
      <dc:creator>Sanket_Parekh</dc:creator>
      <dc:date>2023-05-26T11:40:28Z</dc:date>
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