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    <title>topic how to map cache memory as fast heap in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/how-to-map-cache-memory-as-fast-heap/m-p/1651337#M205969</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I have special algorithm code which is optimized to run many times faster on fast RAM.&lt;/P&gt;&lt;P&gt;Is it possible to map parts of the L1 oder L2 cache of the i.MX8mm SoC to special memory addresses for using it as fast heap memory?&lt;/P&gt;&lt;P&gt;Such things are possible e.g. with TI SysBIOS where you can define parts of the cache memory as Fast RAM with special addresses. Then firmware can consider that for putting code or variables there which much speeds up algorithms.&lt;/P&gt;&lt;P&gt;I don't know if the i.MX8mm provides that in general, and I don't know how to configure that on building the embedded Linux.&lt;/P&gt;&lt;P&gt;Thanx in advance&lt;/P&gt;&lt;P&gt;fbre&lt;/P&gt;</description>
    <pubDate>Tue, 16 May 2023 15:58:47 GMT</pubDate>
    <dc:creator>fbre</dc:creator>
    <dc:date>2023-05-16T15:58:47Z</dc:date>
    <item>
      <title>how to map cache memory as fast heap</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/how-to-map-cache-memory-as-fast-heap/m-p/1651337#M205969</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;I have special algorithm code which is optimized to run many times faster on fast RAM.&lt;/P&gt;&lt;P&gt;Is it possible to map parts of the L1 oder L2 cache of the i.MX8mm SoC to special memory addresses for using it as fast heap memory?&lt;/P&gt;&lt;P&gt;Such things are possible e.g. with TI SysBIOS where you can define parts of the cache memory as Fast RAM with special addresses. Then firmware can consider that for putting code or variables there which much speeds up algorithms.&lt;/P&gt;&lt;P&gt;I don't know if the i.MX8mm provides that in general, and I don't know how to configure that on building the embedded Linux.&lt;/P&gt;&lt;P&gt;Thanx in advance&lt;/P&gt;&lt;P&gt;fbre&lt;/P&gt;</description>
      <pubDate>Tue, 16 May 2023 15:58:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/how-to-map-cache-memory-as-fast-heap/m-p/1651337#M205969</guid>
      <dc:creator>fbre</dc:creator>
      <dc:date>2023-05-16T15:58:47Z</dc:date>
    </item>
    <item>
      <title>Re: how to map cache memory as fast heap</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/how-to-map-cache-memory-as-fast-heap/m-p/1652148#M206045</link>
      <description>&lt;P&gt;Hello&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/151973"&gt;@fbre&lt;/a&gt;&amp;nbsp;,&amp;nbsp;&lt;/P&gt;
&lt;P&gt;We have not documentation about&amp;nbsp;TI SysBIOS, but you can look in the ARM documentation for those functions of L1 and L2 Cache, maybe you can find more information there.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Best regards!&lt;/P&gt;</description>
      <pubDate>Wed, 17 May 2023 14:31:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/how-to-map-cache-memory-as-fast-heap/m-p/1652148#M206045</guid>
      <dc:creator>Manuel_Salas</dc:creator>
      <dc:date>2023-05-17T14:31:41Z</dc:date>
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