EIM Memory location and Multi Buffer

villager — Mon, 15 May 2023 23:57:31 GMT

hello.
We are using imx6 and fpga connected by EIM bus.
When an interrupt occurs in the cpu, the data of CS0 is read from EIM Memory.
The structure is similar to the link below.
https://community.nxp.com/t5/i-MX-Processors/How-to-inteface-an-Xilinx-Artix-FPGA-to-the-imx6-dual-qud/m-p/357941

We basically allocated CS0 as a 128M area.

I have a question.
1) Where is the physical location of this 128MB EIM memory?
Is it the internal memory of imx6 or the internal memory of fpga? Or is it external DDR memory?

2) We are using CS0 as a single buffer.
I want to use multi buffer like Ring buffer.
How do I start implementing it as a Ring buffer?
I would appreciate it if you could let me know the related application note or technical link.

Thank you so much, villager

Re: EIM Memory location and Multi Buffer

jimmychan — Thu, 18 May 2023 08:39:06 GMT

For the EIM details, please read the EIM chapter 22 in the RM.

i.MX 6Dual/6Quad Applications Processor Reference Manual

And you could find some examples from google search about access external memory on EIM.

e.g.

https://community.toradex.com/t/accessing-external-memory-bus-eim-on-imx6-via-memory-map/6831

https://community.toradex.com/t/external-memory-bus-eim-on-imx6/6116

i.MX ProcessorsのトピックEIM Memory location and Multi Buffer

EIM Memory location and Multi Buffer

Re: EIM Memory location and Multi Buffer

i.MX 6Dual/6Quad Applications Processor Reference Manual