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    <title>i.MX Processors中的主题 Re: imx8mp CSI-2 frame start issue</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-CSI-2-frame-start-issue/m-p/1648419#M205658</link>
    <description>&lt;DIV&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/210439"&gt;@Jayden_Soon&lt;/a&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;I hope you are doing well.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Is there any update from your side?&lt;/DIV&gt;
&lt;DIV&gt;If there isn't any query should I proceed to close this thread?&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Thanks &amp;amp; Regards&lt;/DIV&gt;
&lt;DIV&gt;Sanket Parekh&lt;/DIV&gt;
&lt;P&gt;&lt;LI-WRAPPER&gt;&lt;/LI-WRAPPER&gt;&lt;/P&gt;</description>
    <pubDate>Thu, 11 May 2023 07:30:29 GMT</pubDate>
    <dc:creator>Sanket_Parekh</dc:creator>
    <dc:date>2023-05-11T07:30:29Z</dc:date>
    <item>
      <title>imx8mp CSI-2 frame start issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-CSI-2-frame-start-issue/m-p/1639440#M204757</link>
      <description>&lt;P&gt;I am developing a 2-channel camera with DART-MX8M-PLUS.&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;CAM -&amp;gt; PR2000K(HD Receiver with MIPI output) -&amp;gt; imx8mp&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;PR2000K only supports clock continuous mode. No non-continuous mode.&lt;/P&gt;&lt;P&gt;csi2-0&amp;nbsp;works normally, but csi2-1 cannot get a start frame.&amp;nbsp;Strangely, sometimes it works.&lt;/P&gt;&lt;P&gt;Below are the dts file settings.&lt;/P&gt;&lt;TABLE border="1" width="100%"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD width="100%"&gt;&lt;P&gt;pr2000k_mipi1: pr2000k_mipi@5c {&lt;BR /&gt;&amp;nbsp; compatible = "pixelplus,pr2000k";&lt;BR /&gt;&amp;nbsp; reg = &amp;lt;0x5c&amp;gt;;&lt;BR /&gt;&amp;nbsp; clocks = &amp;lt;&amp;amp;clk IMX8MP_CLK_IPP_DO_CLKO2&amp;gt;;&lt;BR /&gt;&amp;nbsp; clock-names = "xclk";&lt;BR /&gt;&amp;nbsp; csi_id = &amp;lt;1&amp;gt;;&lt;BR /&gt;&amp;nbsp; mipi_csi;&lt;BR /&gt;&amp;nbsp; status = "okay";&lt;/P&gt;&lt;P&gt;&amp;nbsp; port {&lt;BR /&gt;&amp;nbsp; &amp;nbsp; pr2000k_mipi_1_ep: endpoint {&lt;BR /&gt;&amp;nbsp; &amp;nbsp; remote-endpoint = &amp;lt;&amp;amp;mipi_csi1_ep&amp;gt;;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; data-lanes = &amp;lt;1 2 3 4&amp;gt;;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; clock-lanes = &amp;lt;0&amp;gt;;&lt;BR /&gt;&amp;nbsp; };&lt;BR /&gt;&amp;nbsp;};&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;pr2000k_mipi0: pr2000k_mipi@5f {&lt;BR /&gt;&amp;nbsp; compatible = "pixelplus,pr2000k";&lt;BR /&gt;&amp;nbsp; reg = &amp;lt;0x5f&amp;gt;;&lt;BR /&gt;&amp;nbsp; clocks = &amp;lt;&amp;amp;clk IMX8MP_CLK_IPP_DO_CLKO2&amp;gt;;&lt;BR /&gt;&amp;nbsp; clock-names = "xclk";&lt;BR /&gt;&amp;nbsp; csi_id = &amp;lt;0&amp;gt;;&lt;BR /&gt;&amp;nbsp; mipi_csi;&lt;BR /&gt;&amp;nbsp; status = "okay";&lt;/P&gt;&lt;P&gt;&amp;nbsp; port {&lt;BR /&gt;&amp;nbsp; &amp;nbsp; pr2000k_mipi_0_ep: endpoint {&lt;BR /&gt;&amp;nbsp; &amp;nbsp; remote-endpoint = &amp;lt;&amp;amp;mipi_csi0_ep&amp;gt;;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; data-lanes = &amp;lt;1 2 3 4&amp;gt;;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; clock-lanes = &amp;lt;0&amp;gt;;&lt;BR /&gt;&amp;nbsp; };&lt;BR /&gt;&amp;nbsp;};&lt;BR /&gt;};&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="100%"&gt;&lt;P&gt;&amp;amp;mipi_csi_0 {&lt;BR /&gt;&amp;nbsp; #address-cells = &amp;lt;1&amp;gt;;&lt;BR /&gt;&amp;nbsp; #size-cells = &amp;lt;0&amp;gt;&lt;BR /&gt;&amp;nbsp; status = "okay";&lt;/P&gt;&lt;P&gt;&amp;nbsp; port@0 {&lt;BR /&gt;&amp;nbsp; &amp;nbsp; reg = &amp;lt;0&amp;gt;;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; mipi_csi0_ep: endpoint {&lt;BR /&gt;&amp;nbsp; &amp;nbsp; remote-endpoint = &amp;lt;&amp;amp;pr2000k_mipi_0_ep&amp;gt;;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; data-lanes = &amp;lt;4&amp;gt;;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; csis-hs-settle = &amp;lt;3&amp;gt;;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; csis-clk-settle = &amp;lt;0&amp;gt;;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; csis-wclk;&lt;BR /&gt;&amp;nbsp; };&lt;BR /&gt;&amp;nbsp;};&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;&amp;amp;mipi_csi_1 {&lt;BR /&gt;&amp;nbsp; #address-cells = &amp;lt;1&amp;gt;;&lt;BR /&gt;&amp;nbsp; #size-cells = &amp;lt;0&amp;gt;&lt;BR /&gt;&amp;nbsp; status = "okay";&lt;/P&gt;&lt;P&gt;&amp;nbsp; port@1 {&lt;BR /&gt;&amp;nbsp; &amp;nbsp; reg = &amp;lt;1&amp;gt;;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; mipi_csi1_ep: endpoint {&lt;BR /&gt;&amp;nbsp; &amp;nbsp; remote-endpoint = &amp;lt;&amp;amp;pr2000k_mipi_1_ep&amp;gt;;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; data-lanes = &amp;lt;4&amp;gt;;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; csis-hs-settle = &amp;lt;3&amp;gt;;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; csis-clk-settle = &amp;lt;0&amp;gt;;&lt;BR /&gt;&amp;nbsp; &amp;nbsp; csis-wclk;&lt;BR /&gt;&amp;nbsp; };&lt;BR /&gt;&amp;nbsp;};&lt;BR /&gt;};&lt;/P&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Debug message of imx8-mipi-csi2-sam.c&lt;/P&gt;&lt;P&gt;csi2-1 cannot get a start frame like below.&lt;/P&gt;&lt;TABLE border="1" width="100%"&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD width="100%"&gt;[ 167.160218] mxc-mipi-csi2.0: mipi_csis_s_stream: 1, state: 0x0&lt;BR /&gt;[ 167.160329] mxc-mipi-csi2.0: mipi_csis_imx8mp_phy_reset: bus fmt is 12 bit !&lt;BR /&gt;[ 167.160368] mxc-mipi-csi2.0: fmt: 0x2006, 1280 x 960&lt;BR /&gt;&lt;STRONG&gt;[ 167.160405] mxc-mipi-csi2.0: Frame Start: 1&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;[ 167.160410] mxc-mipi-csi2.0: status: 01000000&lt;/STRONG&gt;&lt;BR /&gt;[ 167.176222] mxc-mipi-csi2.0: --- mipi_csis_s_stream ---&lt;BR /&gt;[ 167.176234] mxc-mipi-csi2.0: CSIS_VERSION[0]: 0x03060301&lt;BR /&gt;[ 167.176241] mxc-mipi-csi2.0: CSIS_CMN_CTRL[4]: 0x00004b05&lt;BR /&gt;[ 167.176247] mxc-mipi-csi2.0: CSIS_CLK_CTRL[8]: 0x000f0000&lt;BR /&gt;[ 167.176252] mxc-mipi-csi2.0: CSIS_INTMSK[10]: 0x0fffff1f&lt;BR /&gt;[ 167.176258] mxc-mipi-csi2.0: CSIS_INTSRC[14]: 0x00000000&lt;BR /&gt;[ 167.176264] mxc-mipi-csi2.0: CSIS_DPHYSTATUS[20]: 0x00000000&lt;BR /&gt;[ 167.176270] mxc-mipi-csi2.0: CSIS_DPHYCTRL[24]: 0x0300001f&lt;BR /&gt;[ 167.176276] mxc-mipi-csi2.0: CSIS_DPHYBCTRL_L[30]: 0x000001f4&lt;BR /&gt;[ 167.176283] mxc-mipi-csi2.0: CSIS_DPHYBCTRL_H[34]: 0x00000000&lt;BR /&gt;[ 167.176289] mxc-mipi-csi2.0: CSIS_DPHYSCTRL_L[38]: 0x00000000&lt;BR /&gt;[ 167.176295] mxc-mipi-csi2.0: CSIS_DPHYSCTRL_H[3c]: 0x00000000&lt;BR /&gt;[ 167.176301] mxc-mipi-csi2.0: CSIS_ISPCONFIG_CH0[40]: 0x00001078&lt;BR /&gt;[ 167.176306] mxc-mipi-csi2.0: CSIS_ISPCONFIG_CH1[50]: 0x000008fd&lt;BR /&gt;[ 167.176313] mxc-mipi-csi2.0: CSIS_ISPCONFIG_CH2[60]: 0x000008fe&lt;BR /&gt;[ 167.176319] mxc-mipi-csi2.0: CSIS_ISPCONFIG_CH3[70]: 0x000008ff&lt;BR /&gt;[ 167.176325] mxc-mipi-csi2.0: CSIS_ISPRESOL_CH0[44]: 0x03c00500&lt;BR /&gt;[ 167.176330] mxc-mipi-csi2.0: CSIS_ISPRESOL_CH1[54]: 0x80008000&lt;BR /&gt;[ 167.176336] mxc-mipi-csi2.0: CSIS_ISPRESOL_CH2[64]: 0x80008000&lt;BR /&gt;[ 167.176342] mxc-mipi-csi2.0: CSIS_ISPRESOL_CH3[74]: 0x80008000&lt;BR /&gt;[ 167.176348] mxc-mipi-csi2.0: CSIS_ISPSYNC_CH0[48]: 0x00000000&lt;BR /&gt;[ 167.176354] mxc-mipi-csi2.0: CSIS_ISPSYNC_CH1[58]: 0x00000000&lt;BR /&gt;[ 167.176359] mxc-mipi-csi2.0: CSIS_ISPSYNC_CH2[68]: 0x00000000&lt;BR /&gt;[ 167.176365] mxc-mipi-csi2.0: CSIS_ISPSYNC_CH3[78]: 0x00000000&lt;BR /&gt;[ 167.176371] mxc-mipi-csi2.0: --- mipi_csis_s_stream ---&lt;BR /&gt;[ 167.176376] mxc-mipi-csi2.0: GPR_GASKET_0_CTRL[60]: 0xffff8000&lt;BR /&gt;[ 167.176384] mxc-mipi-csi2.0: GPR_GASKET_0_HSIZE[64]: 0xffff8000&lt;BR /&gt;[ 167.176389] mxc-mipi-csi2.0: GPR_GASKET_0_VSIZE[68]: 0xffff8000&lt;BR /&gt;[ 167.192412] mxc-mipi-csi2.0: Frame End: 1&lt;BR /&gt;[ 167.192426] mxc-mipi-csi2.0: status: 00100000&lt;BR /&gt;[ 167.193739] mxc-mipi-csi2.0: Frame Start: 2&lt;BR /&gt;[ 167.193752] mxc-mipi-csi2.0: status: 01000000&lt;BR /&gt;[ 167.225753] mxc-mipi-csi2.0: Frame End: 2&lt;BR /&gt;[ 167.225768] mxc-mipi-csi2.0: status: 00100000&lt;BR /&gt;[ 167.227075] mxc-mipi-csi2.0: Frame Start: 3&lt;BR /&gt;[ 167.227090] mxc-mipi-csi2.0: status: 01000000&lt;/TD&gt;&lt;/TR&gt;&lt;TR&gt;&lt;TD width="100%"&gt;[ 202.392216] mxc-mipi-csi2.1: mipi_csis_s_stream: 1, state: 0x0&lt;BR /&gt;[ 202.392333] mxc-mipi-csi2.1: mipi_csis_imx8mp_phy_reset: bus fmt is 12 bit !&lt;BR /&gt;[ 202.392372] mxc-mipi-csi2.1: fmt: 0x2006, 1280 x 960&lt;BR /&gt;[ 202.408216] mxc-mipi-csi2.1: --- mipi_csis_s_stream ---&lt;BR /&gt;[ 202.408228] mxc-mipi-csi2.1: CSIS_VERSION[0]: 0x03060301&lt;BR /&gt;[ 202.408235] mxc-mipi-csi2.1: CSIS_CMN_CTRL[4]: 0x00004b05&lt;BR /&gt;[ 202.408241] mxc-mipi-csi2.1: CSIS_CLK_CTRL[8]: 0x000f0000&lt;BR /&gt;[ 202.408246] mxc-mipi-csi2.1: CSIS_INTMSK[10]: 0x0fffff1f&lt;BR /&gt;[ 202.408252] mxc-mipi-csi2.1: CSIS_INTSRC[14]: 0x00000000&lt;BR /&gt;[ 202.408258] mxc-mipi-csi2.1: CSIS_DPHYSTATUS[20]: 0x000000f2&lt;BR /&gt;[ 202.408266] mxc-mipi-csi2.1: CSIS_DPHYCTRL[24]: 0x0300001f&lt;BR /&gt;[ 202.408271] mxc-mipi-csi2.1: CSIS_DPHYBCTRL_L[30]: 0x000001f4&lt;BR /&gt;[ 202.408279] mxc-mipi-csi2.1: CSIS_DPHYBCTRL_H[34]: 0x00000000&lt;BR /&gt;[ 202.408285] mxc-mipi-csi2.1: CSIS_DPHYSCTRL_L[38]: 0x00000000&lt;BR /&gt;[ 202.408291] mxc-mipi-csi2.1: CSIS_DPHYSCTRL_H[3c]: 0x00000000&lt;BR /&gt;[ 202.408296] mxc-mipi-csi2.1: CSIS_ISPCONFIG_CH0[40]: 0x00001078&lt;BR /&gt;[ 202.408302] mxc-mipi-csi2.1: CSIS_ISPCONFIG_CH1[50]: 0x000008fd&lt;BR /&gt;[ 202.408308] mxc-mipi-csi2.1: CSIS_ISPCONFIG_CH2[60]: 0x000008fe&lt;BR /&gt;[ 202.408314] mxc-mipi-csi2.1: CSIS_ISPCONFIG_CH3[70]: 0x000008ff&lt;BR /&gt;[ 202.408322] mxc-mipi-csi2.1: CSIS_ISPRESOL_CH0[44]: 0x03c00500&lt;BR /&gt;[ 202.408327] mxc-mipi-csi2.1: CSIS_ISPRESOL_CH1[54]: 0x80008000&lt;BR /&gt;[ 202.408335] mxc-mipi-csi2.1: CSIS_ISPRESOL_CH2[64]: 0x80008000&lt;BR /&gt;[ 202.408341] mxc-mipi-csi2.1: CSIS_ISPRESOL_CH3[74]: 0x80008000&lt;BR /&gt;[ 202.408347] mxc-mipi-csi2.1: CSIS_ISPSYNC_CH0[48]: 0x00000000&lt;BR /&gt;[ 202.408353] mxc-mipi-csi2.1: CSIS_ISPSYNC_CH1[58]: 0x00000000&lt;BR /&gt;[ 202.408358] mxc-mipi-csi2.1: CSIS_ISPSYNC_CH2[68]: 0x00000000&lt;BR /&gt;[ 202.408365] mxc-mipi-csi2.1: CSIS_ISPSYNC_CH3[78]: 0x00000000&lt;BR /&gt;[ 202.408371] mxc-mipi-csi2.1: --- mipi_csis_s_stream ---&lt;BR /&gt;[ 202.408376] mxc-mipi-csi2.1: GPR_GASKET_0_CTRL[60]: 0xffff8000&lt;BR /&gt;[ 202.408382] mxc-mipi-csi2.1: GPR_GASKET_0_HSIZE[64]: 0xffff8000&lt;BR /&gt;[ 202.408388] mxc-mipi-csi2.1: GPR_GASKET_0_VSIZE[68]: 0xffff8000&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-dual-MIPI-camera-CSI-2-1-not-leaving-ULPS-state/m-p/1566842#M198520" target="_self"&gt;https://community.nxp.com/t5/i-MX-Processors/i-MX8M-Plus-dual-MIPI-camera-CSI-2-1-not-leaving-ULPS-state/m-p/1566842#M198520&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;This is similar to the post above.&lt;/P&gt;&lt;P&gt;Are both 2 channels not captured in continuous mode?&lt;/P&gt;&lt;P&gt;Should I redesign with a different receiver chip?&lt;/P&gt;&lt;P&gt;Thanks in advance.&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Jayden&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 03 May 2023 23:55:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-CSI-2-frame-start-issue/m-p/1639440#M204757</guid>
      <dc:creator>Jayden_Soon</dc:creator>
      <dc:date>2023-05-03T23:55:16Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp CSI-2 frame start issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-CSI-2-frame-start-issue/m-p/1641926#M204995</link>
      <description>&lt;DIV&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/210439"&gt;@Jayden_Soon&lt;/a&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;I hope you are doing well&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Kindly mention your BSP version.&lt;/DIV&gt;
&lt;DIV&gt;Are you using the csi2-0 and csi2-1 simultaneously?&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Thanks &amp;amp; Regards,&lt;/DIV&gt;
&lt;DIV&gt;Sanket Parekh&lt;/DIV&gt;</description>
      <pubDate>Fri, 28 Apr 2023 03:48:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-CSI-2-frame-start-issue/m-p/1641926#M204995</guid>
      <dc:creator>Sanket_Parekh</dc:creator>
      <dc:date>2023-04-28T03:48:43Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp CSI-2 frame start issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-CSI-2-frame-start-issue/m-p/1641949#M205000</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;SPAN&gt;Sanket,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;SOM : DART-MX8M-PLUS&lt;/P&gt;&lt;P&gt;BSP :&amp;nbsp;Yocto mx8mp-yocto-kirkstone-5.15-2.0.x-v1.2&lt;/P&gt;&lt;P&gt;I'm trying to use&amp;nbsp;&lt;SPAN&gt;the csi2-0 and csi2-1 simultaneously.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Best regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Jayden&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 28 Apr 2023 04:52:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-CSI-2-frame-start-issue/m-p/1641949#M205000</guid>
      <dc:creator>Jayden_Soon</dc:creator>
      <dc:date>2023-04-28T04:52:22Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp CSI-2 frame start issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-CSI-2-frame-start-issue/m-p/1646145#M205408</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/210439"&gt;@Jayden_Soon&lt;/a&gt;,&lt;/P&gt;
&lt;DIV&gt;I hope you are doing well.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Both continuous and non-continuous modes are supported on IMX8MP. But as mentioned in the document&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;A href="https://www.nxp.com/docs/en/application-note/AN13857.pdf" target="_blank" rel="noopener noreferrer" data-saferedirecturl="https://www.google.com/url?q=https://www.nxp.com/docs/en/application-note/AN13857.pdf&amp;amp;source=gmail&amp;amp;ust=1683612539960000&amp;amp;usg=AOvVaw0-Hc8UC3kh2GgeZZWTYi31"&gt;AN13857&lt;/A&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;U&gt;section&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;6.4 Debug tips&lt;/SPAN&gt;,&lt;/U&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;"&lt;SPAN&gt;Note:&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;i.MX 8MM, i.MX 8MN, and i.MX 8MP require the connected camera to work in the LP state before&lt;/SPAN&gt;&lt;BR role="presentation" /&gt;&lt;SPAN&gt;enabling the Rx DPHY. But if the camera works in&amp;nbsp;continuous&amp;nbsp;clock mode, the clock lane may always be in the&lt;/SPAN&gt;&lt;BR role="presentation" /&gt;&lt;SPAN&gt;HS mode. In this case, Rx DPHY may not detect the HS mode and wrongly remains in the stop or ULPS state."&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;Hence, it is recommended to use the clock in non-continuous mode.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Thanks &amp;amp; Regards,&lt;BR /&gt;Sanket Parekh&lt;/DIV&gt;</description>
      <pubDate>Mon, 08 May 2023 06:18:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-CSI-2-frame-start-issue/m-p/1646145#M205408</guid>
      <dc:creator>Sanket_Parekh</dc:creator>
      <dc:date>2023-05-08T06:18:18Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp CSI-2 frame start issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-CSI-2-frame-start-issue/m-p/1646258#M205420</link>
      <description>&lt;P&gt;Hi Sanket,&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;PR2000K(HD Receiver) only supports clock continuous mode.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;It's hard to solve it and looks like I need a little more study.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thank you for reply.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Best regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Jayden&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 08 May 2023 08:15:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-CSI-2-frame-start-issue/m-p/1646258#M205420</guid>
      <dc:creator>Jayden_Soon</dc:creator>
      <dc:date>2023-05-08T08:15:48Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp CSI-2 frame start issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-CSI-2-frame-start-issue/m-p/1648419#M205658</link>
      <description>&lt;DIV&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/210439"&gt;@Jayden_Soon&lt;/a&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;I hope you are doing well.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Is there any update from your side?&lt;/DIV&gt;
&lt;DIV&gt;If there isn't any query should I proceed to close this thread?&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Thanks &amp;amp; Regards&lt;/DIV&gt;
&lt;DIV&gt;Sanket Parekh&lt;/DIV&gt;
&lt;P&gt;&lt;LI-WRAPPER&gt;&lt;/LI-WRAPPER&gt;&lt;/P&gt;</description>
      <pubDate>Thu, 11 May 2023 07:30:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-CSI-2-frame-start-issue/m-p/1648419#M205658</guid>
      <dc:creator>Sanket_Parekh</dc:creator>
      <dc:date>2023-05-11T07:30:29Z</dc:date>
    </item>
    <item>
      <title>Re: imx8mp CSI-2 frame start issue</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx8mp-CSI-2-frame-start-issue/m-p/2054125#M234616</link>
      <description>Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/210439"&gt;@Jayden_Soon&lt;/a&gt;,&lt;BR /&gt;&lt;BR /&gt;I hope you are doing well.&lt;BR /&gt;I am currently working with the PR2000K MIPI camera. If you have the Linux driver code for the PR2000K, it would be very helpful to me.&lt;BR /&gt;&lt;BR /&gt;Thank you!&lt;BR /&gt;</description>
      <pubDate>Sat, 01 Mar 2025 13:07:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx8mp-CSI-2-frame-start-issue/m-p/2054125#M234616</guid>
      <dc:creator>Rosan</dc:creator>
      <dc:date>2025-03-01T13:07:40Z</dc:date>
    </item>
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