i.MX Processors中的主题 Re: Need clarification on timing details of SEMC interface in i.MXRT

Need clarification on timing details of SEMC interface in i.MXRT

sowmiya_a — Wed, 10 May 2023 05:54:59 GMT

Hi,

We are using MIMXRT1024CAG4B in our design and we plan to interface an SDRAM to it.

1. As part of our timing analysis, we need to clarify how the microcontroller writes data to the SDRAM. Does it do so on the falling edge of the clock? can you confirm this detail.

2. Furthermore, we have noticed that the datasheet for the controller specifies a negative data output hold time of -1ns. Can you please explain the significance of this value? Does it imply that the hold time ends before the clock's falling edge? could you confirm if our understanding is correct?

Re: Need clarification on timing details of SEMC interface in i.MXRT

jingpan — Wed, 10 May 2023 08:50:22 GMT

Hi @sowmiya_a ,

1. Please see the timing diagram

2. There is another explain diagram after the table.

Regards,

Jing

Re: Need clarification on timing details of SEMC interface in i.MXRT

sowmiya_a — Thu, 11 May 2023 11:16:13 GMT

Hi,

Thanks for your assistance.

We have already taken the above mentioned timing diagrams into consideration and assumed that the microcontroller writes data into SDRAM in Clock's falling edge for our timing analysis. Can you confirm whether our assumption is accurate?

Re: Need clarification on timing details of SEMC interface in i.MXRT

jingpan — Fri, 12 May 2023 02:08:35 GMT

Hi @sowmiya_a ,

This screenshot is cut from W9812 SDRAM spec. Hope it can be helpful to you.

Regards,

Jing