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    <title>i.MX ProcessorsのトピックRe: Board Info File Location</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Board-Info-File-Location/m-p/1647345#M205548</link>
    <description>&lt;P&gt;Thank you,&amp;nbsp;&lt;SPAN class=""&gt;Bio_TICFSL&lt;/SPAN&gt;&amp;nbsp;.&amp;nbsp; I was discussing this also with a colleague this morning and were also coming to the conclusion that we probably don't need the board info if the device tree is supplying the necessary info.&amp;nbsp; I will go through the setup you have outlined above, probably a few times, and apply it to my setup.&lt;/P&gt;&lt;P&gt;Cheers,&lt;/P&gt;&lt;P&gt;Dana&lt;/P&gt;</description>
    <pubDate>Tue, 09 May 2023 18:41:35 GMT</pubDate>
    <dc:creator>danab</dc:creator>
    <dc:date>2023-05-09T18:41:35Z</dc:date>
    <item>
      <title>Board Info File Location</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Board-Info-File-Location/m-p/1646539#M205460</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I am working on adding a spi-uart bridge.&amp;nbsp; The part vendor has provided a driver and device tree bindings info.&amp;nbsp; The README also includes a structure to add to the board file.&lt;/P&gt;&lt;P&gt;The target hardware is the mx8 nano DDR4 EVK being built under Yocto.&lt;/P&gt;&lt;P&gt;I don't know where the board initialization file is.&amp;nbsp; Is this achieved differently for arm64 devices?&lt;/P&gt;&lt;BLOCKQUOTE&gt;&lt;P&gt;&lt;BR /&gt;If SPI mode is used:&lt;BR /&gt;Define the spi0_board_info object on your board file similar to the following:&lt;BR /&gt;&lt;BR /&gt;i.e.:&lt;BR /&gt;static struct spi_board_info spi0_board_info[] __initdata = {&lt;BR /&gt;{&lt;BR /&gt;...&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;Thanks!&lt;/P&gt;&lt;P&gt;Dana&lt;/P&gt;</description>
      <pubDate>Mon, 08 May 2023 17:46:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Board-Info-File-Location/m-p/1646539#M205460</guid>
      <dc:creator>danab</dc:creator>
      <dc:date>2023-05-08T17:46:30Z</dc:date>
    </item>
    <item>
      <title>Re: Board Info File Location</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Board-Info-File-Location/m-p/1647226#M205537</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;
&lt;P&gt;This steps are similar for MX8MN, This is what you need to do:&lt;/P&gt;
&lt;OL&gt;
&lt;LI&gt;&lt;STRONG&gt;Add SPI port(s) to the file fsl-imx8qm.dts&lt;/STRONG&gt;
&lt;UL&gt;
&lt;LI&gt;&lt;SPAN&gt;The file can be found in the folder &lt;EM&gt; /tmp/work-shared/imx8qmmek/kernel-source/arch/arm64/boot/dts/freescale&lt;/EM&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI&gt;&lt;SPAN&gt;In the current beta-release there is already an entry for the lpspi0&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI&gt;&lt;SPAN&gt;The address of the LPSPI port can be found in the Reference Manual --&amp;gt; System Memory Map --&amp;gt; Audio DMA Memory Maps&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI&gt;&lt;SPAN&gt;There is also an LPSPI peripheral in the i.MX7ULP, so for now you can keep this entry in "compatible". Maybe later on, when the i.MX8 became more popular in the Linux world, there might be other strings.&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI&gt;&lt;SPAN&gt;The defines for the clocks can be found in the file &lt;EM&gt;imx8qm-clock.h&lt;/EM&gt;&lt;/SPAN&gt;&lt;SPAN&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;lpspi0: lpspi@5a000000 {&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;compatible = "fsl,imx7ulp-spi";&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;reg = &amp;lt;0x0 0x5a000000 0x0 0x10000&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;interrupts = &amp;lt;GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;interrupt-parent = &amp;lt;&amp;amp;gic&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;clocks = &amp;lt;&amp;amp;clk IMX8QM_SPI0_CLK&amp;gt;,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp; &amp;lt;&amp;amp;clk IMX8QM_SPI0_IPG_CLK&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;clock-names = "per", "ipg";&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;assigned-clocks = &amp;lt;&amp;amp;clk IMX8QM_SPI0_CLK&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;assigned-clock-rates = &amp;lt;20000000&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;power-domains = &amp;lt;&amp;amp;pd_dma_lpspi0&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;status = "disabled";&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;};&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;lpspi1: lpspi@5a010000 {&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; compatible = "fsl,imx7ulp-spi";&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; reg = &amp;lt;0x0 0x5a010000 0x0 0x10000&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; interrupts = &amp;lt;GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; interrupt-parent = &amp;lt;&amp;amp;gic&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; clocks = &amp;lt;&amp;amp;clk IMX8QM_SPI1_CLK&amp;gt;,&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;lt;&amp;amp;clk IMX8QM_SPI1_IPG_CLK&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; clock-names = "per", "ipg";&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; assigned-clocks = &amp;lt;&amp;amp;clk IMX8QM_SPI1_CLK&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; assigned-clock-rates = &amp;lt;20000000&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; power-domains = &amp;lt;&amp;amp;pd_dma_lpspi1&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; status = "disabled";&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp; };&lt;BR /&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/LI&gt;
&lt;/UL&gt;
&lt;/LI&gt;
&lt;LI&gt;&lt;STRONG&gt;You need to define the pins for the SPI ports you want to use.&lt;/STRONG&gt;
&lt;OL&gt;
&lt;LI&gt;There is an example for the lpspi0 in the file &lt;EM&gt;fsl-imx8qm-lpddr4-arm2-lpspi.dts&lt;/EM&gt; in the folder&lt;EM&gt; /tmp/work-shared/imx8qmmek/kernel-source/arch/arm64/boot/dts/freescale&lt;BR /&gt;&lt;BR /&gt;&lt;/EM&gt;&lt;SPAN&gt;&amp;amp;iomuxc {&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;imx8qm-arm2 {&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;pinctrl_lpspi0: lpspi0grp {&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;fsl,pins = &amp;lt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;SC_P_SPI0_SCK_DMA_SPI0_SCK&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;0x0600004c&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;SC_P_SPI0_SDO_DMA_SPI0_SDO&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;0x0600004c&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;SC_P_SPI0_SDI_DMA_SPI0_SDI&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;0x0600004c&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;};&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;pinctrl_lpspi0_cs: lpspi0cs {&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;fsl,pins = &amp;lt;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;SC_P_SPI0_CS0_LSIO_GPIO3_IO05&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;0x21&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;};&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;};&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;amp;lpspi0 {&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;#address-cells = &amp;lt;1&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;#size-cells = &amp;lt;0&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;fsl,spi-num-chipselects = &amp;lt;1&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;pinctrl-names = "default";&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;pinctrl-0 = &amp;lt;&amp;amp;pinctrl_lpspi0 &amp;amp;pinctrl_lpspi0_cs&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;cs-gpios = &amp;lt;&amp;amp;gpio3 5 GPIO_ACTIVE_LOW&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;status = "okay";&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;flash: at45db041e@0 {&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;#address-cells = &amp;lt;1&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;#size-cells = &amp;lt;1&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;compatible = "atmel,at45", "atmel,dataflash";&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;spi-max-frequency = &amp;lt;500000&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; &amp;nbsp;reg = &amp;lt;0&amp;gt;;&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; };&lt;/SPAN&gt;&lt;BR /&gt;&lt;SPAN&gt;};&lt;/SPAN&gt;&lt;EM&gt;&lt;BR /&gt;&lt;/EM&gt;&lt;/LI&gt;
&lt;/OL&gt;
&lt;/LI&gt;
&lt;LI&gt;&lt;STRONG&gt;Configure the Kernel config for SPI support&lt;/STRONG&gt;
&lt;UL&gt;
&lt;LI&gt;Please check if the Kernel config file contains the following defines:&lt;BR /&gt;CONFIG_SPI=y&lt;BR /&gt;CONFIG_SPI_IMX=y&lt;BR /&gt;CONFIG_SPI_FSL_LPSPI=y&lt;/LI&gt;
&lt;LI&gt;If you want this as a default Kernel config setting, please edit the file &lt;EM&gt;defconfig&lt;/EM&gt; in the folder &lt;EM&gt;/tmp/work-shared/imx8qmmek/kernel-source/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig&lt;BR /&gt;&lt;/EM&gt;&lt;/LI&gt;
&lt;/UL&gt;
&lt;/LI&gt;
&lt;LI&gt;&lt;STRONG&gt;Test the SPI port&lt;/STRONG&gt;
&lt;UL&gt;
&lt;LI&gt;After creating an image you can test the SPI port on device level and on hardware level&lt;/LI&gt;
&lt;LI&gt;To load the SPI driver on command line:&amp;nbsp; &lt;SPAN&gt;$ modprobe spidev&lt;/SPAN&gt;&lt;/LI&gt;
&lt;LI&gt;The standard SPI driver in the Linux Kernel (spi-imx.c) would allow you to use the port and finally you should see something on the port when you try to send data.&lt;/LI&gt;
&lt;/UL&gt;
&lt;/LI&gt;
&lt;/OL&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;I need to admit that at the time of writing I didn't test it on the 8MN board, so if you can't make it working please come back to me and I will give it a try on my side.&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Regards,&lt;/P&gt;</description>
      <pubDate>Tue, 09 May 2023 14:29:45 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Board-Info-File-Location/m-p/1647226#M205537</guid>
      <dc:creator>Bio_TICFSL</dc:creator>
      <dc:date>2023-05-09T14:29:45Z</dc:date>
    </item>
    <item>
      <title>Re: Board Info File Location</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Board-Info-File-Location/m-p/1647345#M205548</link>
      <description>&lt;P&gt;Thank you,&amp;nbsp;&lt;SPAN class=""&gt;Bio_TICFSL&lt;/SPAN&gt;&amp;nbsp;.&amp;nbsp; I was discussing this also with a colleague this morning and were also coming to the conclusion that we probably don't need the board info if the device tree is supplying the necessary info.&amp;nbsp; I will go through the setup you have outlined above, probably a few times, and apply it to my setup.&lt;/P&gt;&lt;P&gt;Cheers,&lt;/P&gt;&lt;P&gt;Dana&lt;/P&gt;</description>
      <pubDate>Tue, 09 May 2023 18:41:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Board-Info-File-Location/m-p/1647345#M205548</guid>
      <dc:creator>danab</dc:creator>
      <dc:date>2023-05-09T18:41:35Z</dc:date>
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