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    <title>i.MX ProcessorsのトピックRe: iMX8MP IBIS Model Selection</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX8MP-IBIS-Model-Selection/m-p/1647310#M205545</link>
    <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Thank you for your interest in NXP Semiconductor products,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;The documentation within the ZIP file cannot be extended, it has already all the information regarding IBIS simulation for the device,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Based on RGMII unique pins, SAI1_TXD2 and SAI1_RXD6, respectively AH11 and AH10, this is the model to be used.&lt;/SPAN&gt;&lt;/P&gt;
&lt;LI-CODE lang="markup"&gt;[Pin]   Signal_name          model_name             R_pin     L_pin      C_pin

AH10 SAI1_RXD6 PBIDIRHS_E33_33_NT_DR_H 0.40338 2.23E-09 8.88E-13                                 enet1.RGMII_RD2

AH11 SAI1_TXD2 PBIDIRHS_E33_33_NT_DR_H 0.34821 1.99E-09 8.54E-13                                 enet1.RGMII_TD2&lt;/LI-CODE&gt;
&lt;P&gt;Then, that is the model to be used, mapped through the desired pads and as seen, the model to be used is the same for TX and RX pins.&lt;/P&gt;
&lt;P&gt;Thank you!&lt;/P&gt;</description>
    <pubDate>Tue, 09 May 2023 17:32:11 GMT</pubDate>
    <dc:creator>JosephAtNXP</dc:creator>
    <dc:date>2023-05-09T17:32:11Z</dc:date>
    <item>
      <title>iMX8MP IBIS Model Selection</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8MP-IBIS-Model-Selection/m-p/1640030#M204821</link>
      <description>&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;I'm currently using an iMX8M Plus in a design an attempting to do a signal integrity analysis on my RGMII lines.&amp;nbsp; There's not much documentation included in the IBIS zip file so i'm looking for clarification on what pin model i should be using on my RXD and TXD pins.&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;</description>
      <pubDate>Tue, 25 Apr 2023 20:57:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8MP-IBIS-Model-Selection/m-p/1640030#M204821</guid>
      <dc:creator>michaelperreca</dc:creator>
      <dc:date>2023-04-25T20:57:29Z</dc:date>
    </item>
    <item>
      <title>Re: iMX8MP IBIS Model Selection</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8MP-IBIS-Model-Selection/m-p/1647310#M205545</link>
      <description>&lt;P&gt;Hi,&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Thank you for your interest in NXP Semiconductor products,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;The documentation within the ZIP file cannot be extended, it has already all the information regarding IBIS simulation for the device,&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Based on RGMII unique pins, SAI1_TXD2 and SAI1_RXD6, respectively AH11 and AH10, this is the model to be used.&lt;/SPAN&gt;&lt;/P&gt;
&lt;LI-CODE lang="markup"&gt;[Pin]   Signal_name          model_name             R_pin     L_pin      C_pin

AH10 SAI1_RXD6 PBIDIRHS_E33_33_NT_DR_H 0.40338 2.23E-09 8.88E-13                                 enet1.RGMII_RD2

AH11 SAI1_TXD2 PBIDIRHS_E33_33_NT_DR_H 0.34821 1.99E-09 8.54E-13                                 enet1.RGMII_TD2&lt;/LI-CODE&gt;
&lt;P&gt;Then, that is the model to be used, mapped through the desired pads and as seen, the model to be used is the same for TX and RX pins.&lt;/P&gt;
&lt;P&gt;Thank you!&lt;/P&gt;</description>
      <pubDate>Tue, 09 May 2023 17:32:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8MP-IBIS-Model-Selection/m-p/1647310#M205545</guid>
      <dc:creator>JosephAtNXP</dc:creator>
      <dc:date>2023-05-09T17:32:11Z</dc:date>
    </item>
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