topic Re: IMX8MP and DSI errata in i.MX Processors

IMX8MP and DSI errata

tylernol — Fri, 28 Apr 2023 21:03:10 GMT

hi there , I am bringing up a 1080x2160 panel with the IMX8MP and am encountering what appears to be hsync issues Digging through the sec-dsim.c bridge code, I see the following notes:

https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/drivers/gpu/drm/bridge/sec-dsim.c#L1621

```

/* workaround for CEA standard mode "1280x720@60" "1920x1080p24"

* display on 4 data lanes with Non-burst with sync

* pulse DSI mode, since use the standard horizontal

* timings cannot display correctly. And this code

* cannot be put into the dsim Bridge's mode_fixup,

* since the DSI device lane number change always

* happens after that.

```

is there errata for this bug ?

Re: IMX8MP and DSI errata

joanxie — Sat, 29 Apr 2023 01:08:54 GMT

what display do you use? did you use MIPI DSI or HDMI port?

Re: IMX8MP and DSI errata

tylernol — Sat, 29 Apr 2023 14:52:44 GMT

MIPI DSI, thanks.

Re: IMX8MP and DSI errata

tylernol — Mon, 01 May 2023 19:34:14 GMT

also when I look at the programming guide for the DSI I see a note saying the max resolution is "1-2047" . Is that correct? Or is is really 4095? There appear to be 12 bits allocated?

this is from "

i.MX 8M Plus Applications Processor Reference Manual, Rev. 1, 06/2021"

Re: IMX8MP and DSI errata

joanxie — Thu, 04 May 2023 05:29:29 GMT

refer to the reference manual:

This chip supports one 4-lane MIPI DSI display with pixels from the LCDIF. The
key features of the MIPI DSI (controller and PHY) include:
• Compliant to MIPI-DSI standard v1.2
• Support up to 4 data lanes
• Maximum resolution limited to resolutions achievable with a 250MHz pixel
clock and active pixel rate of 200Mpixel/s with 24-bit RGB. This includes
resolutions such as:
• 1080 p60
• WUXGA (1920x1200) at 60 Hz
• 1920x1440 at 60 Hz
• UWHD (2560x1080) at 60 Hz
• WQHD (2560x1440) can be supported by reduced blanking mode

so 1080x2160 should be supported, what kind of hsync issue do you get? did you measure pixel clock?

Re: IMX8MP and DSI errata

tylernol — Thu, 04 May 2023 15:52:48 GMT

it is strobing horizontal bars over the image, I can update a video . I will also measure the actual bit clock, the pixel clock is 135466, which becomes a bit clock of 812796. In the LUT for the mphy, the bsearch yields the entry for 810, which appears to have the same settings as 820, so I am wondering if the bit clock is running a bit faster than expected. I will get a measure of the actual DSI clock today as well.

Re: IMX8MP and DSI errata

tylernol — Thu, 04 May 2023 22:45:53 GMT

the documentation does not quite seem to match the implementation for the PLL programming. When the row for 810 is selected, what FOUT frequency should be generated here?

Re: IMX8MP and DSI errata

tylernol — Fri, 05 May 2023 23:33:14 GMT

here is a capture of what the video looks like .

Re: IMX8MP and DSI errata

tylernol — Fri, 05 May 2023 23:38:26 GMT

we have not measured the MIPI clock yet. Getting that wired up by Monday. Is there any documentation on how the "

13.7.2.14.3.1 Timing Control Register of High-Speed Data Transmission" registers are set? I'd like to understand the results we get when the sec-dsim driver looks up in dphy_timing_ln14lpp_v1p2

Re: IMX8MP and DSI errata

joanxie — Sat, 06 May 2023 05:09:29 GMT

for timing, you can refer to the document as below to understand

“https://community.nxp.com/docs/DOC-345307”

firstly I suggest that you need to know what your display pixel clock, then check if current adv7535 can support it or no, pls check structure valid_clocks from

"linux-imx/adv7511_drv.c at lf-6.1.y · nxp-imx/linux-imx · GitHub"

if not, pls add new pixel clock there, the pixel clock is from video_pll1_out, you can find it from dtsi file, this clock is defined from imx_pll1443x_tbl as below

"linux-imx/clk-pll14xx.c at lf-6.1.y · nxp-imx/linux-imx · GitHub"

this pll clock(pllout) Formula :
• FOUT=((m + k/65536) × FIN) / (p × 2s)
• Where, 1 ≤ p ≤ 63, 64 ≤ m ≤ 1023, 0 ≤ s ≤ 6, -32768 ≤ k ≤ 32767

hope these are helpful for you

Re: IMX8MP and DSI errata

tylernol — Mon, 08 May 2023 23:56:58 GMT

for the MIPI DSI PHY (MPHY) , sec-dsim.c , both in the code and the documentation, the settings seem a bit different. It has P, M, and S, but no K. Is that correct?

https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/drivers/gpu/drm/bridge/sec-dsim.c#L212

https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/drivers/gpu/drm/bridge/sec-dsim.c#L1281

thanks!

Re: IMX8MP and DSI errata

joanxie — Tue, 09 May 2023 04:42:01 GMT

it's ok, don't need k, you can just consider the forum as

PLL Fout = Fin * M/(p*2^s)

Re: IMX8MP and DSI errata

tylernol — Tue, 09 May 2023 16:40:25 GMT

alright I have a pixel clock that works out well for the PLL divider computation: pixel = 135500000, bit = 812400000(m = 677, p = 1-. s= 0). However there is also the DPHY timing lookup:

https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/drivers/gpu/drm/imx/sec_mipi_dphy_ln14lpp.h#LL21C1-L21C1

that bit clock will match against the "810" entry:

https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/drivers/gpu/drm/imx/sec_mipi_dphy_ln14lpp.h#L151

if you look at adjacent entries, it is the same timing clues as 800 and 820. What is the programming/doc guide for this part?

thanks!

Re: IMX8MP and DSI errata

joanxie — Tue, 16 May 2023 07:28:42 GMT

you can refer to the code as below:

"https://github.com/nxp-imx/linux-imx/blob/lf-6.1.y/drivers/clk/imx/clk-pll14xx.c"