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    <title>i.MX ProcessorsのトピックI.MAX8MQ LPDDR4-3200 3G solution</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/I-MAX8MQ-LPDDR4-3200-3G-solution/m-p/1641928#M204997</link>
    <description>&lt;P&gt;We use LPDDR4-3200, 3G Memory applied in I.MAX8MQ (MIMX8MQ6DVAJZAB).&lt;/P&gt;&lt;P&gt;Can please provide the latest collocation scheme or list for all particle suggestions about LPDDR4-3200 3G for "Row 16bit"?&lt;/P&gt;</description>
    <pubDate>Fri, 28 Apr 2023 03:55:40 GMT</pubDate>
    <dc:creator>Tyler_Chen</dc:creator>
    <dc:date>2023-04-28T03:55:40Z</dc:date>
    <item>
      <title>I.MAX8MQ LPDDR4-3200 3G solution</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I-MAX8MQ-LPDDR4-3200-3G-solution/m-p/1641928#M204997</link>
      <description>&lt;P&gt;We use LPDDR4-3200, 3G Memory applied in I.MAX8MQ (MIMX8MQ6DVAJZAB).&lt;/P&gt;&lt;P&gt;Can please provide the latest collocation scheme or list for all particle suggestions about LPDDR4-3200 3G for "Row 16bit"?&lt;/P&gt;</description>
      <pubDate>Fri, 28 Apr 2023 03:55:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I-MAX8MQ-LPDDR4-3200-3G-solution/m-p/1641928#M204997</guid>
      <dc:creator>Tyler_Chen</dc:creator>
      <dc:date>2023-04-28T03:55:40Z</dc:date>
    </item>
    <item>
      <title>Re: I.MAX8MQ LPDDR4-3200 3G solution</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I-MAX8MQ-LPDDR4-3200-3G-solution/m-p/1642129#M205027</link>
      <description>&lt;P&gt;for row 16, pls refer to:&lt;/P&gt;
&lt;P&gt;"The memory vendors often do not offer so many variants of single-channel memory&lt;BR /&gt;devices. As an alternative, a dual-channel device with only one channel connected&lt;BR /&gt;may be used. For example:&lt;BR /&gt;A dual-rank, single-channel device with 16-row address bits has a density of 16Gb.&lt;BR /&gt;If such a device is not available at the chosen supplier, a dual-rank, dual-channel&lt;BR /&gt;device with 16-row address bits can be used instead. This device has a density of&lt;BR /&gt;32 Gb however since only one channel can be connected to the SoC, only half of the&lt;BR /&gt;density is available (16 Gb).&lt;BR /&gt;Usage of more than one discrete memory chips to overcome market constraints is not&lt;BR /&gt;supported since only point-to-point connections are assumed for LPDDR4."&lt;/P&gt;</description>
      <pubDate>Fri, 28 Apr 2023 08:29:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I-MAX8MQ-LPDDR4-3200-3G-solution/m-p/1642129#M205027</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2023-04-28T08:29:31Z</dc:date>
    </item>
    <item>
      <title>Re: I.MAX8MQ LPDDR4-3200 3G solution</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/I-MAX8MQ-LPDDR4-3200-3G-solution/m-p/1642828#M205108</link>
      <description>&lt;P&gt;Hello Joanxie&lt;BR /&gt;Thanks for your feedback, I understand your description&lt;BR /&gt;However, our products have already been mass-produced and the Layout cannot be modified.&lt;BR /&gt;Need 16-bit help for LPDDR4 Row address official certified list or actual case (3Gb or 6Gb) at the moment, or can any support for LPDDR4 model names about (AVL) or any other suggestions?&lt;/P&gt;&lt;P&gt;*Our target is I.MAX8M with 3G memory&lt;/P&gt;</description>
      <pubDate>Tue, 02 May 2023 09:26:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/I-MAX8MQ-LPDDR4-3200-3G-solution/m-p/1642828#M205108</guid>
      <dc:creator>Tyler_Chen</dc:creator>
      <dc:date>2023-05-02T09:26:17Z</dc:date>
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