topic Re: DMA SMFC Channel Flexibility in i.MX Processors

DMA SMFC Channel Flexibility

AlejandroS — Thu, 20 Apr 2023 18:10:56 GMT

Hi,

This is a question regarding the DMA SMFC Channels. I'm using a SabreSD Quad Platform with Android Pie.

Typically (as shown in the picture below) the sensor connected to CSI0 sends the data through the dma_smfc_ch0.

I would like to know if it's possible to configure the data path for CSI1 to make the flow go through dma_smfc_ch0 as well, instead of any other channel, since my understanding is that dma_smfc_ch0 is the only channel that is able to use the whole FIFO, while the other channels will use a reduced FIFO.

To provide more context, currently, our application is running intensive operations in memory, so we need to have a FIFO as big as possible to queue data so that the camera pixels are not lost while the memory is busy, so I appreciate it if anyone can provide more input on this and/or there are other ideas.

Re: DMA SMFC Channel Flexibility

Bio_TICFSL — Thu, 20 Apr 2023 20:32:17 GMT

Hello,

From camera SMFC can use only one DMA channel. "DI (data identifier)" concept is used

only for MIPI interface, this is described in sect.37.4. i.MX 6Dual/6Quad Applications Processor Reference Manual

Regards

Re: DMA SMFC Channel Flexibility

AlejandroS — Fri, 21 Apr 2023 22:29:58 GMT

@Bio_TICFSL Thanks for the timely reply!

Moreover, from table IPUx_SMFC_MAP field descriptions I see (for instance):

My understanding is that one can map CSI1 data to DMASMFC channel 0. This way the data would be mapped to the FIFO base address 0 which is what we need.

Is there anything else I'm missing that won't enable us to make this configuration?