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    <title>topic Re: IMX8 eMMC CMD timing in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX8-eMMC-CMD-timing/m-p/1637462#M204535</link>
    <description>&lt;P&gt;The design is working though so, is there a violation? it doesn't make sense that the JEDEC standard calls out that they are edge aligned, but then the processor needs a setup and hold time.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can you please help me understand this?&lt;/P&gt;</description>
    <pubDate>Thu, 20 Apr 2023 17:57:22 GMT</pubDate>
    <dc:creator>reickhoff</dc:creator>
    <dc:date>2023-04-20T17:57:22Z</dc:date>
    <item>
      <title>IMX8 eMMC CMD timing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8-eMMC-CMD-timing/m-p/1630556#M203958</link>
      <description>&lt;P&gt;Using the IMX8SXL with HS400&amp;nbsp;@167MHz&lt;/P&gt;&lt;DIV&gt;- The table only calls out SDR50 for setup and hold is this valid for SDR104?&lt;/DIV&gt;&lt;DIV&gt;- Can you confirm that we are understanding our plots (below) correctly? the cursors should show a setup of ~ 4.68ns (pass) and a hold of ~1.12ns (fail). Everything has been working fine, and we are confident in our constraint routing from NXP.&lt;/DIV&gt;&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="reickhoff_4-1681133831340.png" style="width: 438px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/218540iAC0AD82E81C11F6B/image-dimensions/438x109?v=v2" width="438" height="109" role="button" title="reickhoff_4-1681133831340.png" alt="reickhoff_4-1681133831340.png" /&gt;&lt;/span&gt;&lt;BR /&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="reickhoff_3-1681133803387.png" style="width: 452px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/218539i444BCE324E69C703/image-dimensions/452x438?v=v2" width="452" height="438" role="button" title="reickhoff_3-1681133803387.png" alt="reickhoff_3-1681133803387.png" /&gt;&lt;/span&gt;&lt;/DIV&gt;&lt;DIV&gt;We also got the clock, cmd, and strobe captured on one plot&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV&gt;BLUE=CLK&amp;nbsp; &amp;nbsp;/&amp;nbsp; &amp;nbsp;ORANGE=STROBE&amp;nbsp; &amp;nbsp;/&amp;nbsp; &amp;nbsp;YELLOW=CMD&lt;/DIV&gt;&lt;DIV&gt;&lt;DIV class=""&gt;&amp;nbsp;&lt;/DIV&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="reickhoff_5-1681133986049.png" style="width: 542px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/218543i911D71C5B7C185DC/image-dimensions/542x336?v=v2" width="542" height="336" role="button" title="reickhoff_5-1681133986049.png" alt="reickhoff_5-1681133986049.png" /&gt;&lt;/span&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;/DIV&gt;&lt;/DIV&gt;</description>
      <pubDate>Mon, 10 Apr 2023 13:43:35 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8-eMMC-CMD-timing/m-p/1630556#M203958</guid>
      <dc:creator>reickhoff</dc:creator>
      <dc:date>2023-04-10T13:43:35Z</dc:date>
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    <item>
      <title>Re: IMX8 eMMC CMD timing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8-eMMC-CMD-timing/m-p/1631403#M204028</link>
      <description>&lt;P&gt;Hello!&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;The uSDHC Input Setup Time and uSDHC Input HoldTime for SDR50&amp;nbsp; and SDR104 should be the same for the &lt;STRONG&gt;IMX8DXL&lt;/STRONG&gt; (I guess you are using it). Answering your question, yes, your understanding is the correct.&lt;/P&gt;
&lt;P&gt;Best regards&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/198302"&gt;@reickhoff&lt;/a&gt;&amp;nbsp;.&lt;/P&gt;</description>
      <pubDate>Tue, 11 Apr 2023 14:33:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8-eMMC-CMD-timing/m-p/1631403#M204028</guid>
      <dc:creator>Manuel_Salas</dc:creator>
      <dc:date>2023-04-11T14:33:48Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8 eMMC CMD timing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8-eMMC-CMD-timing/m-p/1631407#M204030</link>
      <description>&lt;P&gt;So there is a violation? how is that possible if the data is coming back sync'd with the strobe and we have adhered to the routing constraints?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 11 Apr 2023 14:50:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8-eMMC-CMD-timing/m-p/1631407#M204030</guid>
      <dc:creator>reickhoff</dc:creator>
      <dc:date>2023-04-11T14:50:50Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8 eMMC CMD timing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8-eMMC-CMD-timing/m-p/1637462#M204535</link>
      <description>&lt;P&gt;The design is working though so, is there a violation? it doesn't make sense that the JEDEC standard calls out that they are edge aligned, but then the processor needs a setup and hold time.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Can you please help me understand this?&lt;/P&gt;</description>
      <pubDate>Thu, 20 Apr 2023 17:57:22 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8-eMMC-CMD-timing/m-p/1637462#M204535</guid>
      <dc:creator>reickhoff</dc:creator>
      <dc:date>2023-04-20T17:57:22Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8 eMMC CMD timing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8-eMMC-CMD-timing/m-p/1638180#M204616</link>
      <description>&lt;P&gt;Hello!&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;In datasheet the&amp;nbsp;SDR104 mode the timing parameters are defined with the SCK as a reference. But the CMD must be referenced to STROBE, please check the figure 10.10.3 from&amp;nbsp;JESD84-B51 and table 218 HS400 CMD RESPONSE TIMING.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Conclusion, please refer to the&amp;nbsp;&lt;SPAN&gt;JESD84-B51 and not to datasheet because I believe in datasheet is a typo.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&lt;SPAN&gt;Best regards!&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Fri, 21 Apr 2023 16:51:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8-eMMC-CMD-timing/m-p/1638180#M204616</guid>
      <dc:creator>Manuel_Salas</dc:creator>
      <dc:date>2023-04-21T16:51:11Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8 eMMC CMD timing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8-eMMC-CMD-timing/m-p/1638977#M204710</link>
      <description>&lt;P&gt;To confirm, you are saying there is a datasheet typo and that our timing looks correct?&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;</description>
      <pubDate>Mon, 24 Apr 2023 13:05:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8-eMMC-CMD-timing/m-p/1638977#M204710</guid>
      <dc:creator>reickhoff</dc:creator>
      <dc:date>2023-04-24T13:05:42Z</dc:date>
    </item>
    <item>
      <title>Re: IMX8 eMMC CMD timing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX8-eMMC-CMD-timing/m-p/1639116#M204724</link>
      <description>&lt;P&gt;That is correct, and your timings looks OK according to the&amp;nbsp;&lt;SPAN&gt;JESD84-B51.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;Best regards.&lt;/P&gt;</description>
      <pubDate>Mon, 24 Apr 2023 17:53:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX8-eMMC-CMD-timing/m-p/1639116#M204724</guid>
      <dc:creator>Manuel_Salas</dc:creator>
      <dc:date>2023-04-24T17:53:14Z</dc:date>
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