<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>topic i.MX8MP USB 2.0/3.0 usage in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-USB-2-0-3-0-usage/m-p/1635506#M204379</link>
    <description>&lt;P&gt;Hi all, I'm working through a design and wanted to get some clarification on the USB ports on the iMX8M PLUS mcu. I see that it has 4 separate PHYs, two USB2 and 2 USB3. Can those ports be used completely separately? As in, can I connect two USB 2 devices and 2 USB 3 devices (for a total of four different devices) at once? Additionally, do the paired USB 2.0/3.0 PHYs share bandwidth in any internal upstream interface? If I saturate USB 3.0 port 1, could I end up starving USB 2.0 port 1 of bandwidth?&lt;/P&gt;&lt;P&gt;Thank you&lt;/P&gt;</description>
    <pubDate>Tue, 18 Apr 2023 14:48:37 GMT</pubDate>
    <dc:creator>kccarpenter</dc:creator>
    <dc:date>2023-04-18T14:48:37Z</dc:date>
    <item>
      <title>i.MX8MP USB 2.0/3.0 usage</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-USB-2-0-3-0-usage/m-p/1635506#M204379</link>
      <description>&lt;P&gt;Hi all, I'm working through a design and wanted to get some clarification on the USB ports on the iMX8M PLUS mcu. I see that it has 4 separate PHYs, two USB2 and 2 USB3. Can those ports be used completely separately? As in, can I connect two USB 2 devices and 2 USB 3 devices (for a total of four different devices) at once? Additionally, do the paired USB 2.0/3.0 PHYs share bandwidth in any internal upstream interface? If I saturate USB 3.0 port 1, could I end up starving USB 2.0 port 1 of bandwidth?&lt;/P&gt;&lt;P&gt;Thank you&lt;/P&gt;</description>
      <pubDate>Tue, 18 Apr 2023 14:48:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-USB-2-0-3-0-usage/m-p/1635506#M204379</guid>
      <dc:creator>kccarpenter</dc:creator>
      <dc:date>2023-04-18T14:48:37Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8MP USB 2.0/3.0 usage</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-USB-2-0-3-0-usage/m-p/1643949#M205186</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/216011"&gt;@kccarpenter&lt;/a&gt;,&lt;/P&gt;&lt;P&gt;Please accept my apologies for the delayed reply.&lt;BR /&gt;&lt;BR /&gt;Based on the iMX8MPlus Reference Manual this processor has 2 USB 3.0 Phys&lt;BR /&gt;However, these 2 ports support both USB 2.0, and USB 3.0 speeds. Here are the specifications for this module and specifications for USB 2.0 and USB 3.0:&lt;BR /&gt;&lt;BR /&gt;"The USB 3.0 PHY supports the USB 3.0 SuperSpeed (5 Gbps) protocol and data rate and is backward compatible with USB 2.0 high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) protocols and data rates."&lt;BR /&gt;&lt;BR /&gt;Related to your question about using 4 ports. As I mentioned this processor has only 2 PHYs but can support four programmable, bidirectional USB endpoints. Means that these 4 endpoints' communications share bandwidth and electric characteristics.&lt;BR /&gt;You can program using the Universal Serial Bus Controller section in the iMX8MPlus Reference Manual.&lt;/P&gt;&lt;P&gt;Best regards, Brian.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 03 May 2023 20:10:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-USB-2-0-3-0-usage/m-p/1643949#M205186</guid>
      <dc:creator>brian14</dc:creator>
      <dc:date>2023-05-03T20:10:20Z</dc:date>
    </item>
  </channel>
</rss>

