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    <title>i.MX Processorsのトピックhow to increase sclk frequency</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/how-to-increase-sclk-frequency/m-p/1634654#M204307</link>
    <description>&lt;P&gt;the provided structure as below there no variable for sclk inreame as of now iam generating 1mhz but i need to generate 10mhz to 15mhz&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Processor&lt;/STRONG&gt;: mimxrt1170&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;IDE&lt;/STRONG&gt;:MCUXpresso IDE v11.6.0 [Build 8187] [2022-07-13]&lt;/P&gt;&lt;P&gt;/*! @brief LPSPI master configuration structure.*/&lt;BR /&gt;typedef struct _lpspi_master_config&lt;BR /&gt;{&lt;BR /&gt;uint32_t baudRate; /*!&amp;lt; Baud Rate for LPSPI. */&lt;BR /&gt;uint32_t bitsPerFrame; /*!&amp;lt; Bits per frame, minimum 8, maximum 4096.*/&lt;BR /&gt;lpspi_clock_polarity_t cpol; /*!&amp;lt; Clock polarity. */&lt;BR /&gt;lpspi_clock_phase_t cpha; /*!&amp;lt; Clock phase. */&lt;BR /&gt;lpspi_shift_direction_t direction; /*!&amp;lt; MSB or LSB data shift direction. */&lt;/P&gt;&lt;P&gt;uint32_t pcsToSckDelayInNanoSec; /*!&amp;lt; PCS to SCK delay time in nanoseconds, setting to 0 sets the minimum delay.&lt;BR /&gt;It sets the boundary value if out of range.*/&lt;BR /&gt;uint32_t lastSckToPcsDelayInNanoSec; /*!&amp;lt; Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum&lt;BR /&gt;delay. It sets the boundary value if out of range.*/&lt;BR /&gt;uint32_t betweenTransferDelayInNanoSec; /*!&amp;lt; After the SCK delay time with nanoseconds, setting to 0 sets the&lt;BR /&gt;minimum delay. It sets the boundary value if out of range.*/&lt;/P&gt;&lt;P&gt;lpspi_which_pcs_t whichPcs; /*!&amp;lt; Desired Peripheral Chip Select (PCS). */&lt;BR /&gt;lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!&amp;lt; Desired PCS active high or low */&lt;/P&gt;&lt;P&gt;lpspi_pin_config_t pinCfg; /*!&amp;lt; Configures which pins are used for input and output data&lt;BR /&gt;*during single bit transfers.*/&lt;/P&gt;&lt;P&gt;lpspi_data_out_config_t dataOutConfig; /*!&amp;lt; Configures if the output data is tristated&lt;BR /&gt;* between accesses (LPSPI_PCS is negated). */&lt;BR /&gt;}&lt;/P&gt;</description>
    <pubDate>Mon, 17 Apr 2023 12:01:42 GMT</pubDate>
    <dc:creator>sandeep_c</dc:creator>
    <dc:date>2023-04-17T12:01:42Z</dc:date>
    <item>
      <title>how to increase sclk frequency</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/how-to-increase-sclk-frequency/m-p/1634654#M204307</link>
      <description>&lt;P&gt;the provided structure as below there no variable for sclk inreame as of now iam generating 1mhz but i need to generate 10mhz to 15mhz&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Processor&lt;/STRONG&gt;: mimxrt1170&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;IDE&lt;/STRONG&gt;:MCUXpresso IDE v11.6.0 [Build 8187] [2022-07-13]&lt;/P&gt;&lt;P&gt;/*! @brief LPSPI master configuration structure.*/&lt;BR /&gt;typedef struct _lpspi_master_config&lt;BR /&gt;{&lt;BR /&gt;uint32_t baudRate; /*!&amp;lt; Baud Rate for LPSPI. */&lt;BR /&gt;uint32_t bitsPerFrame; /*!&amp;lt; Bits per frame, minimum 8, maximum 4096.*/&lt;BR /&gt;lpspi_clock_polarity_t cpol; /*!&amp;lt; Clock polarity. */&lt;BR /&gt;lpspi_clock_phase_t cpha; /*!&amp;lt; Clock phase. */&lt;BR /&gt;lpspi_shift_direction_t direction; /*!&amp;lt; MSB or LSB data shift direction. */&lt;/P&gt;&lt;P&gt;uint32_t pcsToSckDelayInNanoSec; /*!&amp;lt; PCS to SCK delay time in nanoseconds, setting to 0 sets the minimum delay.&lt;BR /&gt;It sets the boundary value if out of range.*/&lt;BR /&gt;uint32_t lastSckToPcsDelayInNanoSec; /*!&amp;lt; Last SCK to PCS delay time in nanoseconds, setting to 0 sets the minimum&lt;BR /&gt;delay. It sets the boundary value if out of range.*/&lt;BR /&gt;uint32_t betweenTransferDelayInNanoSec; /*!&amp;lt; After the SCK delay time with nanoseconds, setting to 0 sets the&lt;BR /&gt;minimum delay. It sets the boundary value if out of range.*/&lt;/P&gt;&lt;P&gt;lpspi_which_pcs_t whichPcs; /*!&amp;lt; Desired Peripheral Chip Select (PCS). */&lt;BR /&gt;lpspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!&amp;lt; Desired PCS active high or low */&lt;/P&gt;&lt;P&gt;lpspi_pin_config_t pinCfg; /*!&amp;lt; Configures which pins are used for input and output data&lt;BR /&gt;*during single bit transfers.*/&lt;/P&gt;&lt;P&gt;lpspi_data_out_config_t dataOutConfig; /*!&amp;lt; Configures if the output data is tristated&lt;BR /&gt;* between accesses (LPSPI_PCS is negated). */&lt;BR /&gt;}&lt;/P&gt;</description>
      <pubDate>Mon, 17 Apr 2023 12:01:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/how-to-increase-sclk-frequency/m-p/1634654#M204307</guid>
      <dc:creator>sandeep_c</dc:creator>
      <dc:date>2023-04-17T12:01:42Z</dc:date>
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