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    <title>i.MX ProcessorsのトピックRe: i.MX8MP Memory Device Tree Configuration</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-Memory-Device-Tree-Configuration/m-p/1634637#M204304</link>
    <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/206842"&gt;@Wobaffet&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;I hope you are doing well.&lt;/P&gt;
&lt;P&gt;One can define memory node for&amp;nbsp;&lt;SPAN&gt;512MB LPDDR4 DRAM in dts as below.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;LI-CODE lang="c"&gt;memory@40000000 {
      device_type = "memory";
      reg = &amp;lt;0x0 0x40000000 0 0x20000000&amp;gt;;
};&lt;/LI-CODE&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Additional changes are also required for 512MB DRAM in u-boot-imx.&lt;/P&gt;
&lt;P&gt;In the board configuration header file. (/include/configs/..)&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;LI-CODE lang="markup"&gt;#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x2000000&lt;/LI-CODE&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Please refer to&amp;nbsp;5.7 Adding OP-TEE support for a new board in&amp;nbsp;&lt;A href="https://www.nxp.com/docs/en/user-guide/IMX_PORTING_GUIDE.pdf" target="_self"&gt;i.MX Porting Guide&lt;/A&gt;&amp;nbsp;and change&amp;nbsp;CFG_DDR_SIZE (if op-tee is used.)&lt;/P&gt;
&lt;P&gt;Thanks &amp;amp; Regards,&lt;BR /&gt;Dhruvit Vasavada&lt;/P&gt;</description>
    <pubDate>Mon, 17 Apr 2023 11:40:57 GMT</pubDate>
    <dc:creator>Dhruvit</dc:creator>
    <dc:date>2023-04-17T11:40:57Z</dc:date>
    <item>
      <title>i.MX8MP Memory Device Tree Configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-Memory-Device-Tree-Configuration/m-p/1633931#M204234</link>
      <description>&lt;P&gt;Hello, For our custom board, we'll have 512MB LPDDR4 &lt;SPAN&gt;&lt;SPAN class=""&gt;MT53E128M32D2DS-046&lt;/SPAN&gt;&lt;/SPAN&gt; from micron. In the EVK DT, 6GB memory configured as follows:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="markup"&gt;        memory@40000000 {
                device_type = "memory";
                reg = &amp;lt;0x0 0x40000000 0 0xc0000000&amp;gt;,
                      &amp;lt;0x1 0x00000000 0 0xc0000000&amp;gt;;
        };&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;According to memory mapping from Reference Manual of the processor DDR addressing is like this:&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper lia-image-align-inline" image-alt="Wobaffet_0-1681478650778.png" style="width: 637px;"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/219299iDEB39050D4153D3F/image-dimensions/637x56?v=v2" width="637" height="56" role="button" title="Wobaffet_0-1681478650778.png" alt="Wobaffet_0-1681478650778.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;So can I configure for our board like this:&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="markup"&gt;        memory@40000000 {
                device_type = "memory";
                reg = &amp;lt;0x0 0x40000000 0 0x20000000&amp;gt;;
        };&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;or do I need to configure like this?&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;LI-CODE lang="markup"&gt;        memory@40000000 {  
                device_type = "memory";
                reg = &amp;lt;0x0 0x40000000 0 0x10000000&amp;gt;,
                      &amp;lt;0x1 0x00000000 0 0x10000000&amp;gt;;
        };&lt;/LI-CODE&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Fri, 14 Apr 2023 13:30:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-Memory-Device-Tree-Configuration/m-p/1633931#M204234</guid>
      <dc:creator>Wobaffet</dc:creator>
      <dc:date>2023-04-14T13:30:29Z</dc:date>
    </item>
    <item>
      <title>Re: i.MX8MP Memory Device Tree Configuration</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-Memory-Device-Tree-Configuration/m-p/1634637#M204304</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/206842"&gt;@Wobaffet&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;I hope you are doing well.&lt;/P&gt;
&lt;P&gt;One can define memory node for&amp;nbsp;&lt;SPAN&gt;512MB LPDDR4 DRAM in dts as below.&lt;/SPAN&gt;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;LI-CODE lang="c"&gt;memory@40000000 {
      device_type = "memory";
      reg = &amp;lt;0x0 0x40000000 0 0x20000000&amp;gt;;
};&lt;/LI-CODE&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Additional changes are also required for 512MB DRAM in u-boot-imx.&lt;/P&gt;
&lt;P&gt;In the board configuration header file. (/include/configs/..)&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;LI-CODE lang="markup"&gt;#define PHYS_SDRAM 0x40000000
#define PHYS_SDRAM_SIZE 0x2000000&lt;/LI-CODE&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;&amp;nbsp;&lt;/P&gt;
&lt;P&gt;Please refer to&amp;nbsp;5.7 Adding OP-TEE support for a new board in&amp;nbsp;&lt;A href="https://www.nxp.com/docs/en/user-guide/IMX_PORTING_GUIDE.pdf" target="_self"&gt;i.MX Porting Guide&lt;/A&gt;&amp;nbsp;and change&amp;nbsp;CFG_DDR_SIZE (if op-tee is used.)&lt;/P&gt;
&lt;P&gt;Thanks &amp;amp; Regards,&lt;BR /&gt;Dhruvit Vasavada&lt;/P&gt;</description>
      <pubDate>Mon, 17 Apr 2023 11:40:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/i-MX8MP-Memory-Device-Tree-Configuration/m-p/1634637#M204304</guid>
      <dc:creator>Dhruvit</dc:creator>
      <dc:date>2023-04-17T11:40:57Z</dc:date>
    </item>
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