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    <title>i.MX ProcessorsのトピックRe: Problem Using UART6 RX on CSI_PIXCLK</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Problem-Using-UART6-RX-on-CSI-PIXCLK/m-p/1634276#M204258</link>
    <description>&lt;P&gt;I am just using simple IAR code to test ports (hello world).&amp;nbsp; Not using DTS or Linux or ENET2, or anything else.&amp;nbsp; I do not need RTS or CTS, I just want to transmit and receive from this port.&lt;/P&gt;</description>
    <pubDate>Mon, 17 Apr 2023 02:33:40 GMT</pubDate>
    <dc:creator>jautry</dc:creator>
    <dc:date>2023-04-17T02:33:40Z</dc:date>
    <item>
      <title>Problem Using UART6 RX on CSI_PIXCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Problem-Using-UART6-RX-on-CSI-PIXCLK/m-p/1633491#M204184</link>
      <description>&lt;P&gt;I am using the CSI_PIXCLK line for UART6 RX but am having problems with receiving any data.&amp;nbsp; The TX line on CSI_MCLK works fine.&amp;nbsp; I am working with an MCIMX6Y2DVM05AB processor.&amp;nbsp; Is there any errata that pertains to this?&lt;/P&gt;&lt;P&gt;Initialization Code:&lt;/P&gt;&lt;P&gt;IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK = IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_MUX_MODE(8) \&lt;BR /&gt;| (0&amp;lt;&amp;lt;IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_SION_SHIFT);&lt;BR /&gt;&lt;BR /&gt;IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK = IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_MUX_MODE(8) \&lt;BR /&gt;| (0&amp;lt;&amp;lt;IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_SION_SHIFT);&lt;BR /&gt;IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK = 0x10B0;&lt;BR /&gt;IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK = 0x1090;&lt;BR /&gt;&lt;BR /&gt;IOMUXC_UART6_RX_DATA_SELECT_INPUT = IOMUXC_UART6_RX_DATA_SELECT_INPUT_DAISY(3);&lt;/P&gt;</description>
      <pubDate>Fri, 14 Apr 2023 02:17:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Problem-Using-UART6-RX-on-CSI-PIXCLK/m-p/1633491#M204184</guid>
      <dc:creator>jautry</dc:creator>
      <dc:date>2023-04-14T02:17:33Z</dc:date>
    </item>
    <item>
      <title>Re: Problem Using UART6 RX on CSI_PIXCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Problem-Using-UART6-RX-on-CSI-PIXCLK/m-p/1634270#M204257</link>
      <description>&lt;P&gt;pls check this document, to check if your settings has any pins conflict and check your dts settings&lt;/P&gt;
&lt;P&gt;"&lt;A href="https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/How-To-use-UART7-8-on-i-MX6UL/ta-p/1099593" target="_blank"&gt;https://community.nxp.com/t5/i-MX-Processors-Knowledge-Base/How-To-use-UART7-8-on-i-MX6UL/ta-p/1099593&lt;/A&gt;"&lt;/P&gt;</description>
      <pubDate>Mon, 17 Apr 2023 02:21:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Problem-Using-UART6-RX-on-CSI-PIXCLK/m-p/1634270#M204257</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2023-04-17T02:21:36Z</dc:date>
    </item>
    <item>
      <title>Re: Problem Using UART6 RX on CSI_PIXCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Problem-Using-UART6-RX-on-CSI-PIXCLK/m-p/1634276#M204258</link>
      <description>&lt;P&gt;I am just using simple IAR code to test ports (hello world).&amp;nbsp; Not using DTS or Linux or ENET2, or anything else.&amp;nbsp; I do not need RTS or CTS, I just want to transmit and receive from this port.&lt;/P&gt;</description>
      <pubDate>Mon, 17 Apr 2023 02:33:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Problem-Using-UART6-RX-on-CSI-PIXCLK/m-p/1634276#M204258</guid>
      <dc:creator>jautry</dc:creator>
      <dc:date>2023-04-17T02:33:40Z</dc:date>
    </item>
    <item>
      <title>Re: Problem Using UART6 RX on CSI_PIXCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Problem-Using-UART6-RX-on-CSI-PIXCLK/m-p/1642190#M205039</link>
      <description>&lt;P&gt;did you use M core with SDK?&lt;/P&gt;</description>
      <pubDate>Fri, 28 Apr 2023 10:27:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Problem-Using-UART6-RX-on-CSI-PIXCLK/m-p/1642190#M205039</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2023-04-28T10:27:24Z</dc:date>
    </item>
    <item>
      <title>Re: Problem Using UART6 RX on CSI_PIXCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Problem-Using-UART6-RX-on-CSI-PIXCLK/m-p/1642192#M205040</link>
      <description />
      <pubDate>Fri, 28 Apr 2023 10:27:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Problem-Using-UART6-RX-on-CSI-PIXCLK/m-p/1642192#M205040</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2023-04-28T10:27:44Z</dc:date>
    </item>
    <item>
      <title>Re: Problem Using UART6 RX on CSI_PIXCLK</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Problem-Using-UART6-RX-on-CSI-PIXCLK/m-p/1642302#M205051</link>
      <description>&lt;P&gt;Not using M core, I spoke with IAR as the ports worked in other test apps.&amp;nbsp; It is a problem with the sample IAR code provided by NXP not being compatible with their latest IAR Workbench release.&amp;nbsp; The ports actually do work.&lt;/P&gt;</description>
      <pubDate>Fri, 28 Apr 2023 13:49:46 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Problem-Using-UART6-RX-on-CSI-PIXCLK/m-p/1642302#M205051</guid>
      <dc:creator>jautry</dc:creator>
      <dc:date>2023-04-28T13:49:46Z</dc:date>
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