https://community.nxp.com/t5/i-MX-Processors/scfw-API/m-p/1632555#M204094 <P>Hello,</P> <P>Yes, interrupts in the chip are managed through two IPs. One of the IP is the GIC-500 from ARM and Interrupt Steer controller and in this case it is linked to GIC-500 implementation from ARM.</P> <P>Best regards.</P> Wed, 12 Apr 2023 20:21:13 GMT JorgeCas 2023-04-12T20:21:13Z https://community.nxp.com/t5/i-MX-Processors/scfw-API/m-p/1632144#M204083 <P>we are using imxqm and trying to suspend the cores and ddr, ew are using&nbsp;sc_pm_set_cpu_resume API to to resume cpu from lp mode, address parameter in the API .. is this the address scfw jumps when GIC interrupt is hit.&nbsp;</P> Wed, 12 Apr 2023 12:41:24 GMT https://community.nxp.com/t5/i-MX-Processors/scfw-API/m-p/1632144#M204083 Lakshmi_AG 2023-04-12T12:41:24Z https://community.nxp.com/t5/i-MX-Processors/scfw-API/m-p/1632555#M204094 <P>Hello,</P> <P>Yes, interrupts in the chip are managed through two IPs. One of the IP is the GIC-500 from ARM and Interrupt Steer controller and in this case it is linked to GIC-500 implementation from ARM.</P> <P>Best regards.</P> Wed, 12 Apr 2023 20:21:13 GMT https://community.nxp.com/t5/i-MX-Processors/scfw-API/m-p/1632555#M204094 JorgeCas 2023-04-12T20:21:13Z