topic Re: DDR Suspend mode in i.MX Processors

DDR Suspend mode

Lakshmi_AG — Wed, 05 Apr 2023 06:09:34 GMT

Hello,

I want to figure out how imx8m low power management is done in DDR during a power glitch.

1. How to command the scu to put DDR to self refresh mode from one of A53.

2. Once DDR is in self refresh mode, will A53 crash if so how to we send command to scu to run DDR in normal mode once good power signal is receivd.

Re: DDR Suspend mode

Zhiming_Liu — Thu, 06 Apr 2023 02:40:13 GMT

From code layer, the DDR self refresh mode is realized by below code in ATF.

https://github.com/nxp-imx/imx-atf/blob/lf_v2.6/plat/imx/imx8m/ddr/dram_retention.c

You can refer the code design.

void self_refresh_enter() { mmio_setbits_32(DDR_SDRAM_CFG_2, BIT(31)); } void self_refresh_exit() { mmio_clrbits_32(DDR_SDRAM_CFG_2,BIT(31)); }

Re: DDR Suspend mode

Lakshmi_AG — Thu, 06 Apr 2023 06:56:36 GMT

Thank you for the quick response.

To my second question,

We are trying to put all cores to suspend and DDR to self refresh mode, so my question in once we put all cores to suspend mode by sending command to SCFW, how to drive DDR to self-refresh mode, can we do same from SCFW or any other approach.

Re: DDR Suspend mode

Zhiming_Liu — Fri, 07 Apr 2023 01:25:40 GMT

Hello @Lakshmi_AG

Which board you are using? From the first description , you are using i.MX8M. But this board doesn't support SCFW. The SCFW is used by i.MX8QM/QXP.

Zhiming

Re: DDR Suspend mode

Lakshmi_AG — Fri, 07 Apr 2023 02:59:00 GMT

imx8qm

Re: DDR Suspend mode

Lakshmi_AG — Wed, 12 Apr 2023 09:27:30 GMT

Still waiting for the response:

We are trying to put all cores(A53) to suspend and DDR to self refresh mode, so my question in once we put all cores to suspend mode by sending command to SCFW, how to drive DDR to self-refresh mode, can we do same from SCFW or any other approach.

And since A53 is in suspend, how to resume to normal on GIC.

Re: DDR Suspend mode

Zhiming_Liu — Thu, 13 Apr 2023 04:05:09 GMT

Interrupts from each subsystem are mapped on both GIC and interrupt steer and have the
same index starting at 32.

Interrupt Steer is used to route interrupts to the two M4 subsystems and the SCU. GIC500 is used to route interrupts to A53 and A72

how to drive DDR to self-refresh mode

--> Please refer these API in sc_fw_port.pdf

And since A53 is in suspend, how to resume to normal on GIC.

-> You can refer imx_domain_suspend_finish function