MX8MP-M7-ENET-ethernet-driver

luk1 — Sat, 01 Apr 2023 03:54:41 GMT

Hello, I have also been developing mx8mp-M7 core Ethernet (tcp) recently. I have migrated lwip from the mimx8qm SDK, but the communication is abnormal. Can you provide some suggestions and guidance?

Re: MX8MP-M7-ENET-ethernet-driver

Rita_Wang — Tue, 04 Apr 2023 08:45:10 GMT

How about the abnormal communication, you'd better show us more information, and software your are using

Re: MX8MP-M7-ENET-ethernet-driver

luk1 — Mon, 10 Apr 2023 04:24:43 GMT

I want to achieve TCP client or TCP server communication through LWIP, but I cannot establish a connection. My phy chip can communicate normally under the Linux driver, so I can troubleshoot hardware issues. The following is my lwip initialization and pin initialization code:

void BOARD_InitPins(void) { /*!< Function assigned for the core: Cortex-M7F[m7] */
IOMUXC_SetPinMux(IOMUXC_UART4_RXD_UART4_RX, 0U);
IOMUXC_SetPinConfig(IOMUXC_UART4_RXD_UART4_RX,
IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PE_MASK);
IOMUXC_SetPinMux(IOMUXC_UART4_TXD_UART4_TX, 0U);
IOMUXC_SetPinConfig(IOMUXC_UART4_TXD_UART4_TX,
IOMUXC_SW_PAD_CTL_PAD_PUE_MASK |
IOMUXC_SW_PAD_CTL_PAD_PE_MASK);

IOMUXC_SetPinMux(IOMUXC_SAI1_RXD2_ENET1_MDC, 0U);
IOMUXC_SetPinMux(IOMUXC_SAI1_RXD3_ENET1_MDIO, 0U);
IOMUXC_SetPinMux(IOMUXC_SAI1_RXD4_ENET1_RGMII_RD0, 0U);
IOMUXC_SetPinMux(IOMUXC_SAI1_RXD5_ENET1_RGMII_RD1, 0U);
IOMUXC_SetPinMux(IOMUXC_SAI1_RXD6_ENET1_RGMII_RD2, 0U);
IOMUXC_SetPinMux(IOMUXC_SAI1_RXD7_ENET1_RGMII_RD3, 0U);
IOMUXC_SetPinMux(IOMUXC_SAI1_TXC_ENET1_RGMII_RXC, 0U);
IOMUXC_SetPinMux(IOMUXC_SAI1_TXFS_ENET1_RGMII_RX_CTL, 0U);
IOMUXC_SetPinMux(IOMUXC_SAI1_TXD0_ENET1_RGMII_TD0, 0U);
IOMUXC_SetPinMux(IOMUXC_SAI1_TXD1_ENET1_RGMII_TD1, 0U);
IOMUXC_SetPinMux(IOMUXC_SAI1_TXD2_ENET1_RGMII_TD2, 0U);
IOMUXC_SetPinMux(IOMUXC_SAI1_TXD3_ENET1_RGMII_TD3, 0U);
IOMUXC_SetPinMux(IOMUXC_SAI1_TXD4_ENET1_RGMII_TX_CTL, 0U);
IOMUXC_SetPinMux(IOMUXC_SAI1_TXD5_ENET1_RGMII_TXC, 0U);
IOMUXC_SetPinMux(IOMUXC_SPDIF_RX_GPIO5_IO04, 0U);

IOMUXC_SetPinConfig(IOMUXC_SAI1_RXD2_ENET1_MDC, 0x3);
IOMUXC_SetPinConfig(IOMUXC_SAI1_RXD3_ENET1_MDIO, 0x3);
IOMUXC_SetPinConfig(IOMUXC_SAI1_RXD4_ENET1_RGMII_RD0, 0x91);
IOMUXC_SetPinConfig(IOMUXC_SAI1_RXD5_ENET1_RGMII_RD1, 0x91);
IOMUXC_SetPinConfig(IOMUXC_SAI1_RXD6_ENET1_RGMII_RD2, 0x91);
IOMUXC_SetPinConfig(IOMUXC_SAI1_RXD7_ENET1_RGMII_RD3, 0x91);
IOMUXC_SetPinConfig(IOMUXC_SAI1_TXC_ENET1_RGMII_RXC, 0x91);
IOMUXC_SetPinConfig(IOMUXC_SAI1_TXFS_ENET1_RGMII_RX_CTL, 0x91);
IOMUXC_SetPinConfig(IOMUXC_SAI1_TXD0_ENET1_RGMII_TD0, 0x1f);
IOMUXC_SetPinConfig(IOMUXC_SAI1_TXD1_ENET1_RGMII_TD1, 0x1f);
IOMUXC_SetPinConfig(IOMUXC_SAI1_TXD2_ENET1_RGMII_TD2, 0x1f);
IOMUXC_SetPinConfig(IOMUXC_SAI1_TXD3_ENET1_RGMII_TD3, 0x1f);
IOMUXC_SetPinConfig(IOMUXC_SAI1_TXD4_ENET1_RGMII_TX_CTL, 0x1f);
IOMUXC_SetPinConfig(IOMUXC_SAI1_TXD5_ENET1_RGMII_TXC, 0x1f);
IOMUXC_SetPinConfig(IOMUXC_SPDIF_RX_GPIO5_IO04, 0x19);

}

int main()

{

EnableIRQ(ENET1_MAC0_Rx_Tx_Done0_IRQn);
EnableIRQ(ENET1_MAC0_Rx_Tx_Done1_IRQn);
EnableIRQ(ENET1_IRQn);
mdioHandle.resource.csrClock_Hz = EXAMPLE_CLOCK_FREQ;
IP4_ADDR(&netif_ipaddr, configIP_ADDR0, configIP_ADDR1, configIP_ADDR2, configIP_ADDR3);
IP4_ADDR(&netif_netmask, configNET_MASK0, configNET_MASK1, configNET_MASK2, configNET_MASK3);
IP4_ADDR(&netif_gw, configGW_ADDR0, configGW_ADDR1, configGW_ADDR2, configGW_ADDR3);
lwip_init();
netif_add(&netif, &netif_ipaddr, &netif_netmask, &netif_gw, &enet_config, EXAMPLE_NETIF_INIT_FN, ethernet_input);
netif_set_default(&netif);
netif_set_up(&netif);
tcpecho_raw_init();
//tcpecho_clent_init();
PRINTF("\r\n************************************************\r\n");
PRINTF(" TCP Echo example\r\n");
PRINTF("************************************************\r\n");
PRINTF(" IPv4 Address : %u.%u.%u.%u\r\n", ((u8_t *)&netif_ipaddr)[0], ((u8_t *)&netif_ipaddr)[1],
((u8_t *)&netif_ipaddr)[2], ((u8_t *)&netif_ipaddr)[3]);
PRINTF(" IPv4 Subnet mask : %u.%u.%u.%u\r\n", ((u8_t *)&netif_netmask)[0], ((u8_t *)&netif_netmask)[1],
((u8_t *)&netif_netmask)[2], ((u8_t *)&netif_netmask)[3]);
PRINTF(" IPv4 Gateway : %u.%u.%u.%u\r\n", ((u8_t *)&netif_gw)[0], ((u8_t *)&netif_gw)[1],
((u8_t *)&netif_gw)[2], ((u8_t *)&netif_gw)[3]);
PRINTF("************************************************\r\n");
delay1();delay1();delay1();delay1();
while (1)
{
ethernetif_input(&netif);
cal_tri_flag = 1;

}

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Re: MX8MP-M7-ENET-ethernet-driver