topic Re: i.MX8MPlus RMII_REF_CLK in i.MX Processors

i.MX8MPlus RMII_REF_CLK

lw1 — Thu, 16 Mar 2023 14:22:03 GMT

The i.MX 8M Plus Applications Processor Data Sheet states, that the SAI1_MCLK pad can be used as RMII reference clock, but the Processor Reference Manual does not provide any information on how to accomplish this.

According to the latter, the SAI1_MCLK pad can be configured as ENET1_TX_CLK and GPR1 Bit 13 should control the direction of the pin, but I could not get any signal out of this pad.

Furthermore the GPR1 description for this bit has a note:

SOI bit for the pad(iomuxc_sw_input_on_pad_enet_td2) should be set also;

which is probably a copy/paste error from the description of Bit 20.

I can only output the RMII_REF_CLK via pad GPIO1_IO00 as ALT1_CCM_ENET_PHY_REF_CLK_ROOT.

Is there any way to get SAI1_MCLK to output a 50MHz RMII clock, or is there an error in the Processor Datasheet?

Re: i.MX8MPlus RMII_REF_CLK

JosephAtNXP — Mon, 20 Mar 2023 01:25:37 GMT

Hi,

As seen on the 8.1 Table it is possible, it is possible and it may be an ALT MODE, in ENET1 section on page 1334 is mentioned SAI1_MCLK as the pad for the REF_CLK.

See that ALT4 in ENET1 section uses SAI pads, so it is possible.

Thank you

Re: i.MX8MPlus RMII_REF_CLK

lw1 — Tue, 21 Mar 2023 07:51:59 GMT

I read what's written in the docs, BUT THAT APPARENTLY DOESN'T MATCH THE REALITY!

The documentation lists the ALT4 function of the SAI1_MCLK pad as ENET1_TX_CLK which usually refers to the RGMII TXC signal and not the RMII REF_CLK.

As stated before THERE IS NO SIGNAL on the SAI1_MCLK pad when configured as ALT4.

Re: i.MX8MPlus RMII_REF_CLK

JosephAtNXP — Thu, 23 Mar 2023 18:16:02 GMT

Please create a new config tools project to see that the SAI1_MCLK pin has the TX_CLK function while the TXC used by the RGMII function is taken by another pin.

Regards

Re: i.MX8MPlus RMII_REF_CLK

lw1 — Fri, 24 Mar 2023 07:32:48 GMT

OK, that produces exactly the same values that I had configured manually, but DOES NOT PRODUCE ANY SIGNAL on the pad!

Can you measure a 50MHz clock on the SAI1_MCLK pad when configured as ENET1_TX_CLK?