IMXRT1171 - Nandflash semc AXI interface access

f_carpana — Thu, 09 Mar 2023 13:49:23 GMT

Dear all,

I'm tring to configure a SkyHigh ONFI Nand flash (cod. S34ML01G3) using SEMC and AXI interface in IMXRT1171 processor.

I'm starting from nandflash_semc example, and modifing some parts, the memory seems to work properly. However, ther's some details that I can't understand, and I would like to ask:

1) Burst Lenght : which value I have to use? In memory datasheet I can't find anythink regarding this field, and also in processor reference manual. Could you please explain better this field? In my projetc burst length is 64, and seems to work, but i would like to understand why.

2) Access to AXI memory: witch data width is the best choice? using a memcpy, the access seems to be 32 byte wide, but it doesn't works always: in my project I have to use 16 byte wide when reading, and 32 byte wide when I write. In this way reading and writing memory is good, but I would like to understand why, and if there is a rule to set it.

3) In my understanding, AXI access automatically add a 05h and E0h commands when read, and 85h command when write. When reading, how the controller know how many bytes it has to read from nand flash device? There a register (if exist, I can't find it), or every access to AXI mapped memory generate a read instruction to nandflash device? May be burst length to handle this?

Thanks in advance for your support.

Best regards

Francesco

Re: IMXRT1171 - Nandflash semc AXI interface access

Omar_Anguiano — Mon, 20 Mar 2023 22:05:29 GMT

Hello
I hope you are well. I will gladly answer your questions:

1) The value depends on your application needs and the device-specific features. The burst is for transmitting/receiving data repeatedly without going through all the steps required to transmit/receive each piece of data in a separate transaction. This may be working due to the page size of your device.

2) It seems that 32bit is only for write on the AXI mode. 16bit is for NAND read.

3) There is no software configuration or polling needed for AXI access. It depends on the memory configuration although to read write you might refer to the semc example from the SDK which makes 32/16/8 bits writes/reads through the AXI.

Best regards,
Omar

i.MX ProcessorsのトピックIMXRT1171 - Nandflash semc AXI interface access

IMXRT1171 - Nandflash semc AXI interface access

Re: IMXRT1171 - Nandflash semc AXI interface access