<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: Add DDR4 memory to imx8mp</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Add-DDR4-memory-to-imx8mp/m-p/1610784#M202425</link>
    <description />
    <pubDate>Tue, 07 Mar 2023 09:34:47 GMT</pubDate>
    <dc:creator>VoVan</dc:creator>
    <dc:date>2023-03-07T09:34:47Z</dc:date>
    <item>
      <title>Add DDR4 memory to imx8mp</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Add-DDR4-memory-to-imx8mp/m-p/1610671#M202411</link>
      <description>&lt;P&gt;We try add DDR4 64 Gb(8Gigabytes) memory to imx8mp - 2 devices 32 Gb(4Gigabytes) each with 2 bank group adresses(K4ABG165WA). We use &lt;SPAN&gt;&lt;FONT&gt;&lt;FONT&gt;MX8M_Plus_DDR4_RPA_v8.xlsx&lt;/FONT&gt;&lt;/FONT&gt;&lt;/SPAN&gt;.&lt;/P&gt;&lt;P&gt;Our configuration:&lt;/P&gt;&lt;P&gt;Memory type:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; DDR4&lt;BR /&gt;Manufacturer:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; Samsung&lt;BR /&gt;Memory part number:&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; K4ABG165WA-MCWE&lt;BR /&gt;DDR4 Density per Device (Gb) &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;nbsp;&amp;nbsp; 16( &lt;STRONG&gt;&amp;gt; 16Gb &lt;SPAN class=""&gt;more impossible to choose&lt;/SPAN&gt;&lt;/STRONG&gt;)!!!&lt;BR /&gt;Number of DDR4 devices per chip select&amp;nbsp; 2&lt;BR /&gt;Density per chip select (Gb):&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 32&lt;BR /&gt;Number of Chip Selects used&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1&lt;BR /&gt;Total DRAM density (Gb)&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 32&lt;BR /&gt;Number of ROW Addresses&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 17&lt;BR /&gt;Number of COLUMN Addresses&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 10&lt;BR /&gt;Number of BANK addresses&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 2&lt;BR /&gt;Number of BANK GROUP addresses&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 2&lt;BR /&gt;Total number of BANKS&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 16&lt;BR /&gt;DDR4 Data Bus width per device&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 16&lt;BR /&gt;Total Data Bus Width&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 32&lt;BR /&gt;Clock Cycle Freq (MHz) &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;&amp;nbsp; 1600&lt;BR /&gt;Clock Cycle Time (ns)&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 0,625&lt;BR /&gt;FREQ1 setpoint Clock Cycle Freq (MHz)&amp;nbsp;&amp;nbsp; 668&lt;BR /&gt;FREQ1 Clock Cycle Time (ns)&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp; 1,49700598802395&lt;/P&gt;&lt;P&gt;With this config we have:&lt;/P&gt;&lt;P&gt;memory set 0x3D400200 32 0x0000001F #DDRC_ADDRMAP0&lt;BR /&gt;memory set 0x3D400204 32 0x003F0909 #DDRC_ADDRMAP1&lt;BR /&gt;memory set 0x3D400208 32 0x00000700 #DDRC_ADDRMAP2&lt;BR /&gt;memory set 0x3D40020C 32 0x00000000 #DDRC_ADDRMAP3&lt;BR /&gt;memory set 0x3D400210 32 0x00001F1F #DDRC_ADDRMAP4&lt;BR /&gt;memory set 0x3D400214 32 0x08080808 #DDRC_ADDRMAP5&lt;BR /&gt;memory set 0x3D400218 32 0x08080808 #DDRC_ADDRMAP6&lt;BR /&gt;memory set 0x3D40021c 32 0x00000F08 #DDRC_ADDRMAP7&lt;BR /&gt;memory set 0x3D400220 32 0x00000801 #DDRC_ADDRMAP8&lt;/P&gt;&lt;P&gt;With this config DDR4 not work properly. U-boot don't load from RAM.&lt;/P&gt;&lt;P&gt;When set Number of BANK GROUP addresses = 1 We have:&lt;/P&gt;&lt;P&gt;memory set 0x3D400200 32 0x0000001F #DDRC_ADDRMAP0&lt;BR /&gt;memory set 0x3D400204 32 0x003F0909 #DDRC_ADDRMAP1&lt;BR /&gt;memory set 0x3D400208 32 0x00000700 #DDRC_ADDRMAP2&lt;BR /&gt;memory set 0x3D40020C 32 0x00000000 #DDRC_ADDRMAP3&lt;BR /&gt;memory set 0x3D400210 32 0x00001F1F #DDRC_ADDRMAP4&lt;BR /&gt;memory set 0x3D400214 32 0x07070707 #DDRC_ADDRMAP5&lt;BR /&gt;memory set 0x3D400218 32 0x07070707 #DDRC_ADDRMAP6&lt;BR /&gt;memory set 0x3D40021c 32 0x00000F07 #DDRC_ADDRMAP7&lt;BR /&gt;memory set 0x3D400220 32 0x00003F01 #DDRC_ADDRMAP8&lt;/P&gt;&lt;P&gt;DDR4 work (only 4Gigabytes: Since there is no bank switching).U-boot load, only 4Gigabytes work properly with mtest, other 4Gigabytes don't work!!!&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Someone checked work of DDR4 memory without chipselect(Number of Chip Selects used = 1) and with switching bank group(Number of BANK GROUP addresses = 2)???&lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Tue, 07 Mar 2023 08:04:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Add-DDR4-memory-to-imx8mp/m-p/1610671#M202411</guid>
      <dc:creator>VoVan</dc:creator>
      <dc:date>2023-03-07T08:04:48Z</dc:date>
    </item>
    <item>
      <title>Re: Add DDR4 memory to imx8mp</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Add-DDR4-memory-to-imx8mp/m-p/1610784#M202425</link>
      <description />
      <pubDate>Tue, 07 Mar 2023 09:34:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Add-DDR4-memory-to-imx8mp/m-p/1610784#M202425</guid>
      <dc:creator>VoVan</dc:creator>
      <dc:date>2023-03-07T09:34:47Z</dc:date>
    </item>
    <item>
      <title>Re: Add DDR4 memory to imx8mp</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Add-DDR4-memory-to-imx8mp/m-p/1612359#M202520</link>
      <description>&lt;P&gt;Hi&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/207124"&gt;@VoVan&lt;/a&gt;,&lt;/P&gt;
&lt;P&gt;I hope you are doing well.&lt;/P&gt;
&lt;P&gt;Have you made any changes to u-boot configuration header file and device tree file?&lt;/P&gt;
&lt;P&gt;Please provide me with u-boot configuration header for the board (e.g. /include/configs/imx8mp_evk.h) for further debugging.&lt;/P&gt;
&lt;P&gt;Thanks &amp;amp; Regards,&lt;BR /&gt;Sanket Parekh&lt;/P&gt;</description>
      <pubDate>Thu, 09 Mar 2023 11:03:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Add-DDR4-memory-to-imx8mp/m-p/1612359#M202520</guid>
      <dc:creator>Sanket_Parekh</dc:creator>
      <dc:date>2023-03-09T11:03:37Z</dc:date>
    </item>
    <item>
      <title>回复： Add DDR4 memory to imx8mp</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Add-DDR4-memory-to-imx8mp/m-p/1612933#M202549</link>
      <description>&lt;P&gt;include/configs/imx8mp_evk.h changes:(CONFIG_TARGET_IMX8MP_DDR4_EVK set in config)&lt;/P&gt;&lt;P&gt;#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK&lt;BR /&gt;#undef PHYS_SDRAM_SIZE&lt;BR /&gt;#undef PHYS_SDRAM_2&lt;BR /&gt;#define PHYS_SDRAM_SIZE 0x100000000 /* 4 GB */&lt;BR /&gt;#define PHYS_SDRAM_2 0x140000000&lt;BR /&gt;#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */&lt;BR /&gt;#else&lt;BR /&gt;#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */&lt;BR /&gt;#endif&lt;/P&gt;&lt;P&gt;Load from UUU:&lt;/P&gt;&lt;P&gt;U-Boot SPL 2020.04-5.4.70-2.3.3+g44f5949dd9 (Mar 09 2023 - 13:48:34 +0000)&lt;BR /&gt;DDRINFO: start DRAM init&lt;BR /&gt;DDRINFO: DRAM rate 3200MTS&lt;BR /&gt;DDRINFO:ddrphy calibration done&lt;BR /&gt;DDRINFO: ddrmix config done&lt;BR /&gt;Normal Boot&lt;BR /&gt;Trying to boot from BOOTROM&lt;BR /&gt;image offset 0x0, pagesize 0x200, ivt offset 0x0&lt;BR /&gt;NOTICE: BL31: v2.2(release):rel_imx_5.4.70_2.3.2_rc1-0-g2a2678646&lt;BR /&gt;NOTICE: BL31: Built : 12:16:55, Feb 17 2023&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;U-Boot 2020.04-5.4.70-2.3.3+g44f5949dd9 (Mar 09 2023 - 13:48:34 +0000)&lt;/P&gt;&lt;P&gt;CPU: i.MX8MP[8] rev1.1 1600 MHz (running at 1200 MHz)&lt;BR /&gt;CPU: Industrial temperature grade (-40C to 105C) at 28C&lt;BR /&gt;Reset cause: POR&lt;BR /&gt;Model: NXP i.MX8MPlus LPDDR4 EVK board&lt;BR /&gt;DRAM: 8 GiB&lt;BR /&gt;TCPC: Vendor ID [0x1fc9], Product ID [0x5110], Addr [I2C2 0x50]&lt;BR /&gt;SNK.Power3.0 on CC1&lt;BR /&gt;PDO 0: type 0, 5000 mV, 3000 mA [E]&lt;BR /&gt;PDO 1: type 0, 9000 mV, 3000 mA []&lt;BR /&gt;PDO 2: type 0, 15000 mV, 3000 mA []&lt;BR /&gt;PDO 3: type 0, 20000 mV, 2250 mA []&lt;BR /&gt;Requesting PDO 3: 20000 mV, 2250 mA&lt;BR /&gt;Source accept request&lt;BR /&gt;PD source ready!&lt;BR /&gt;tcpc_pd_receive_message: Polling ALERT register, TCPC_ALERT_RX_STATUS bit failed, ret = -62&lt;BR /&gt;Power supply on USB2&lt;BR /&gt;TCPC: Vendor ID [0x1fc9], Product ID [0x5110], Addr [I2C1 0x50]&lt;BR /&gt;MMC: FSL_SDHC: 1, FSL_SDHC: 2&lt;BR /&gt;Loading Environment from MMC... *** Warning - bad CRC, using default environment&lt;/P&gt;&lt;P&gt;[*]-Video Link 0Can't find cec device id=0x3c&lt;BR /&gt;fail to probe panel device adv7535@3d&lt;BR /&gt;fail to get display timings&lt;BR /&gt;probe video device failed, ret -19&lt;/P&gt;&lt;P&gt;[0] lcd-controller@32e80000, video&lt;BR /&gt;[1] mipi_dsi@32e60000, video_bridge&lt;BR /&gt;[2] adv7535@3d, panel&lt;BR /&gt;Can't find cec device id=0x3c&lt;BR /&gt;fail to probe panel device adv7535@3d&lt;BR /&gt;fail to get display timings&lt;BR /&gt;probe video device failed, ret -19&lt;BR /&gt;In: serial&lt;BR /&gt;Out: serial&lt;BR /&gt;Err: serial&lt;/P&gt;&lt;P&gt;BuildInfo:&lt;BR /&gt;- ATF 2a26786&lt;BR /&gt;- U-Boot 2020.04-5.4.70-2.3.3+g44f5949dd9&lt;/P&gt;&lt;P&gt;switch to partitions #0, OK&lt;BR /&gt;mmc2(part 0) is current device&lt;BR /&gt;flash target is MMC:2&lt;BR /&gt;Net:&lt;BR /&gt;Error: ethernet@30be0000 address not set.&lt;/P&gt;&lt;P&gt;Error: ethernet@30be0000 address not set.&lt;/P&gt;&lt;P&gt;Error: ethernet@30bf0000 address not set.&lt;/P&gt;&lt;P&gt;Error: ethernet@30bf0000 address not set.&lt;BR /&gt;No ethernet found.&lt;/P&gt;&lt;P&gt;Fastboot: Normal&lt;BR /&gt;Normal Boot&lt;BR /&gt;Hit any key to stop autoboot: 0&lt;BR /&gt;u-boot=&amp;gt;&lt;BR /&gt;u-boot=&amp;gt;&lt;BR /&gt;u-boot=&amp;gt;&lt;BR /&gt;u-boot=&amp;gt;&lt;BR /&gt;u-boot=&amp;gt; mtest 0x60000000 0x190000000&lt;BR /&gt;Testing 60000000 ... 190000000:&lt;BR /&gt;Pattern FFFFFFFFFFFFFFFF Writing... Reading...n: 2&lt;BR /&gt;u-boot=&amp;gt; &amp;lt;INTERRUPT&amp;gt;&lt;BR /&gt;u-boot=&amp;gt; &amp;lt;INTERRUPT&amp;gt;&lt;BR /&gt;u-boot=&amp;gt; &amp;lt;INTERRUPT&amp;gt;&lt;BR /&gt;u-boot=&amp;gt; &amp;lt;INTERRUPT&amp;gt;&lt;BR /&gt;u-boot=&amp;gt; &amp;lt;INTERRUPT&amp;gt;&lt;BR /&gt;u-boot=&amp;gt; &amp;lt;INTERRUPT&amp;gt;&lt;BR /&gt;u-boot=&amp;gt; &amp;lt;INTERRUPT&amp;gt;&lt;BR /&gt;u-boot=&amp;gt; &amp;lt;INTERRUPT&amp;gt;&lt;BR /&gt;u-boot=&amp;gt; mtest 0x60000000 0x200000000&lt;BR /&gt;Testing 60000000 ... 200000000:&lt;BR /&gt;Pattern 00000000 Writing... Reading..."Synchronous Abort" handler, esr 0x96000210&lt;BR /&gt;elr: 000000004020e5a8 lr : 000000004020e568 (reloc)&lt;BR /&gt;elr: 0000000053f225a8 lr : 0000000053f22568&lt;BR /&gt;x0 : 0000000000000001 x1 : 00000000308900b4&lt;BR /&gt;x2 : 000000002bffffff x3 : 0000000000000001&lt;BR /&gt;x4 : 0000000000000020 x5 : 0000000000000000&lt;BR /&gt;x6 : 00000000ffffffd8 x7 : 0000000000000000&lt;BR /&gt;x8 : 0000000051bf70f8 x9 : 00000000ac82ca15&lt;BR /&gt;x10: 00000000ffffffd0 x11: 0000000000000010&lt;BR /&gt;x12: 0000000000000006 x13: 000000000001869f&lt;BR /&gt;x14: 0000000051bf7438 x15: 0000000000000001&lt;BR /&gt;x16: 0000000053f5c948 x17: 00000000000042f0&lt;BR /&gt;x18: 0000000051bffdb8 x19: 000000002c000000&lt;BR /&gt;x20: 0000000200000000 x21: 0000000000000000&lt;BR /&gt;x22: 0000000000000000 x23: 0000000060000000&lt;BR /&gt;x24: 0000000000000001 x25: 0000000053fa4b92&lt;BR /&gt;x26: 0000000053fa4bd6 x27: 0000000060000000&lt;BR /&gt;x28: 00000001c0000000 x29: 0000000051bf7130&lt;/P&gt;&lt;P&gt;Code: 17ffffe2 f8008401 8b180021 17ffffea (f9400382)&lt;BR /&gt;Resetting CPU ...&lt;/P&gt;&lt;P&gt;resetting ...&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;When set 0x3d4000220(ADDRMAP8) to 0x801 by your xls formula - uboot don't load!!! Why 8 set to ADDRMAP_BG_B1&lt;/STRONG&gt;???&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;When set 0x3d4000220(ADDRMAP8) to 0xa01 by set manually - uboot load ok!!! mtest 0x60000000 0x190000000 - work good!!!, but from address 0x200000000 failed!!!&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;How to work with map registers???&lt;/P&gt;&lt;P&gt;memory set 0x3D400200 32 0x0000001F #DDRC_ADDRMAP0&lt;BR /&gt;memory set 0x3D400204 32 0x003F0909 #DDRC_ADDRMAP1&lt;BR /&gt;memory set 0x3D400208 32 0x00000700 #DDRC_ADDRMAP2&lt;BR /&gt;memory set 0x3D40020C 32 0x00000000 #DDRC_ADDRMAP3&lt;BR /&gt;memory set 0x3D400210 32 0x00001F1F #DDRC_ADDRMAP4&lt;BR /&gt;memory set 0x3D400214 32 0x08080808 #DDRC_ADDRMAP5&lt;BR /&gt;memory set 0x3D400218 32 0x08080808 #DDRC_ADDRMAP6&lt;BR /&gt;memory set 0x3D40021c 32 0x00000F08 #DDRC_ADDRMAP7&lt;BR /&gt;memory set 0x3D400220 32 &lt;STRONG&gt;0x00000a01&lt;/STRONG&gt; #DDRC_ADDRMAP8&lt;/P&gt;&lt;P&gt;What registers need to be changed to start working the entire range of memory???(maybe other ADDRMAP registers or something else)???&lt;/P&gt;&lt;P&gt;I already test work DDR4 from 0x6000000 to 0x190000000 by mtest( need work from 0x200000000 to 0x240000000)....&lt;/P&gt;</description>
      <pubDate>Fri, 10 Mar 2023 06:49:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Add-DDR4-memory-to-imx8mp/m-p/1612933#M202549</guid>
      <dc:creator>VoVan</dc:creator>
      <dc:date>2023-03-10T06:49:09Z</dc:date>
    </item>
    <item>
      <title>回复： Add DDR4 memory to imx8mp</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Add-DDR4-memory-to-imx8mp/m-p/1613167#M202571</link>
      <description>&lt;P&gt;Next step:&lt;/P&gt;&lt;P&gt;include/configs/imx8mp_evk.h changes:(CONFIG_TARGET_IMX8MP_DDR4_EVK set in config)&lt;/P&gt;&lt;P&gt;#ifdef CONFIG_TARGET_IMX8MP_DDR4_EVK&lt;BR /&gt;#undef PHYS_SDRAM_SIZE&lt;BR /&gt;#undef PHYS_SDRAM_2&lt;BR /&gt;#define PHYS_SDRAM_SIZE 0x100000000 /* 4 GB */&lt;BR /&gt;#define PHYS_SDRAM_2 0x140000000&lt;BR /&gt;&lt;STRONG&gt;#define PHYS_SDRAM_2_SIZE 0x80000000 /* 2 GB */&lt;/STRONG&gt;&lt;BR /&gt;#else&lt;BR /&gt;#define PHYS_SDRAM_2_SIZE 0xC0000000 /* 3 GB */&lt;BR /&gt;#endif&lt;/P&gt;&lt;P&gt;UUU load:&lt;/P&gt;&lt;P&gt;U-Boot 2020.04-5.4.70-2.3.3+g44f5949dd9 (Mar 10 2023 - 13:24:17 +0000)&lt;/P&gt;&lt;P&gt;CPU: i.MX8MP[8] rev1.1 1600 MHz (running at 1200 MHz)&lt;BR /&gt;CPU: Industrial temperature grade (-40C to 105C) at 46C&lt;BR /&gt;Reset cause: POR&lt;BR /&gt;Model: NXP i.MX8MPlus LPDDR4 EVK board&lt;BR /&gt;&lt;STRONG&gt;DRAM: 6 GiB&lt;/STRONG&gt;&lt;BR /&gt;TCPC: Vendor ID [0x1fc9], Product ID [0x5110], Addr [I2C2 0x50]&lt;BR /&gt;SNK.Power3.0 on CC1&lt;BR /&gt;PDO 0: type 0, 5000 mV, 3000 mA [E]&lt;BR /&gt;PDO 1: type 0, 9000 mV, 3000 mA []&lt;BR /&gt;PDO 2: type 0, 15000 mV, 3000 mA []&lt;BR /&gt;PDO 3: type 0, 20000 mV, 2250 mA []&lt;BR /&gt;Requesting PDO 3: 20000 mV, 2250 mA&lt;BR /&gt;Source accept request&lt;BR /&gt;PD source ready!&lt;BR /&gt;tcpc_pd_receive_message: Polling ALERT register, TCPC_ALERT_RX_STATUS bit failed, ret = -62&lt;BR /&gt;Power supply on USB2&lt;BR /&gt;TCPC: Vendor ID [0x1fc9], Product ID [0x5110], Addr [I2C1 0x50]&lt;BR /&gt;MMC: FSL_SDHC: 1, FSL_SDHC: 2&lt;BR /&gt;Loading Environment from MMC... *** Warning - bad CRC, using default environment&lt;/P&gt;&lt;P&gt;[*]-Video Link 0Can't find cec device id=0x3c&lt;BR /&gt;fail to probe panel device adv7535@3d&lt;BR /&gt;fail to get display timings&lt;BR /&gt;probe video device failed, ret -19&lt;/P&gt;&lt;P&gt;[0] lcd-controller@32e80000, video&lt;BR /&gt;[1] mipi_dsi@32e60000, video_bridge&lt;BR /&gt;[2] adv7535@3d, panel&lt;BR /&gt;Can't find cec device id=0x3c&lt;BR /&gt;fail to probe panel device adv7535@3d&lt;BR /&gt;fail to get display timings&lt;BR /&gt;probe video device failed, ret -19&lt;BR /&gt;In: serial&lt;BR /&gt;Out: serial&lt;BR /&gt;Err: serial&lt;/P&gt;&lt;P&gt;BuildInfo:&lt;BR /&gt;- ATF 2a26786&lt;BR /&gt;- U-Boot 2020.04-5.4.70-2.3.3+g44f5949dd9&lt;/P&gt;&lt;P&gt;switch to partitions #0, OK&lt;BR /&gt;mmc2(part 0) is current device&lt;BR /&gt;flash target is MMC:2&lt;BR /&gt;Net:&lt;BR /&gt;Error: ethernet@30be0000 address not set.&lt;/P&gt;&lt;P&gt;Error: ethernet@30be0000 address not set.&lt;/P&gt;&lt;P&gt;Error: ethernet@30bf0000 address not set.&lt;/P&gt;&lt;P&gt;Error: ethernet@30bf0000 address not set.&lt;BR /&gt;No ethernet found.&lt;/P&gt;&lt;P&gt;Fastboot: Normal&lt;BR /&gt;Normal Boot&lt;BR /&gt;Hit any key to stop autoboot: 0&lt;BR /&gt;u-boot=&amp;gt;&lt;BR /&gt;u-boot=&amp;gt;&lt;BR /&gt;u-boot=&amp;gt;&lt;BR /&gt;u-boot=&amp;gt;&lt;BR /&gt;u-boot=&amp;gt;&lt;BR /&gt;u-boot=&amp;gt;&lt;BR /&gt;u-boot=&amp;gt;&lt;BR /&gt;u-boot=&amp;gt; mtest 60000000 1c0000000&lt;BR /&gt;&lt;STRONG&gt;Testing 60000000 ... 1c0000000:&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;Pattern FFFFFFFFFFFFFFFF Writing... Reading...n: 20: 19&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;u-boot=&amp;gt; run bootcmd&lt;BR /&gt;switch to partitions #0, OK&lt;BR /&gt;mmc2(part 0) is current device&lt;BR /&gt;30931456 bytes read in 170 ms (173.5 MiB/s)&lt;BR /&gt;Booting from mmc ...&lt;BR /&gt;64519 bytes read in 11 ms (5.6 MiB/s)&lt;BR /&gt;## Flattened Device Tree blob at 43000000&lt;BR /&gt;Booting using the fdt blob at 0x43000000&lt;BR /&gt;Using Device Tree in place at 0000000043000000, end 0000000043012c06&lt;BR /&gt;Can't find cec device id=0x3c&lt;BR /&gt;fail to probe panel device adv7535@3d&lt;BR /&gt;fail to get display timings&lt;BR /&gt;probe video device failed, ret -19&lt;/P&gt;&lt;P&gt;Starting kernel ...&lt;/P&gt;&lt;P&gt;[ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x410fd034]&lt;BR /&gt;[ 0.000000] Linux version 5.15.32-lts-next+gfa6c3168595c (oe-user@oe-host) (aarch64-poky-linux-gcc (GCC) 11.2.0, GNU ld (GNU Binutils) 2.38.20220313&lt;BR /&gt;) #1 SMP PREEMPT Tue Jun 7 02:34:46 UTC 2022&lt;BR /&gt;[ 0.000000] Machine model: NXP i.MX8MPlus EVK board&lt;BR /&gt;[ 0.000000] efi: UEFI not found.&lt;BR /&gt;[ 0.000000] Reserved memory: created CMA memory pool at 0x00000000c4000000, size 960 MiB&lt;BR /&gt;[ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool&lt;BR /&gt;[ 0.000000] Reserved memory: created DMA memory pool at 0x0000000094300000, size 1 MiB&lt;BR /&gt;[ 0.000000] OF: reserved mem: initialized node vdev0buffer@94300000, compatible id shared-dma-pool&lt;BR /&gt;[ 0.000000] NUMA: No NUMA configuration found&lt;BR /&gt;[ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x00000001bfffffff]&lt;BR /&gt;[ 0.000000] NUMA: NODE_DATA [mem 0x1bf443800-0x1bf445fff]&lt;BR /&gt;[ 0.000000] Zone ranges:&lt;BR /&gt;[ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]&lt;BR /&gt;[ 0.000000] DMA32 empty&lt;BR /&gt;[ 0.000000] Normal [mem 0x0000000100000000-0x00000001bfffffff]&lt;BR /&gt;[ 0.000000] Movable zone start for each node&lt;BR /&gt;[ 0.000000] Early memory node ranges&lt;BR /&gt;[ 0.000000] node 0: [mem 0x0000000040000000-0x0000000055ffffff]&lt;BR /&gt;[ 0.000000] node 0: [mem 0x0000000058000000-0x00000000923fffff]&lt;BR /&gt;[ 0.000000] node 0: [mem 0x0000000092400000-0x00000000a43fffff]&lt;BR /&gt;[ 0.000000] node 0: [mem 0x00000000a4400000-0x00000001bfffffff]&lt;BR /&gt;[ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x00000001bfffffff]&lt;BR /&gt;[ 0.000000] psci: probing for conduit method from DT.&lt;BR /&gt;[ 0.000000] psci: PSCIv1.1 detected in firmware.&lt;BR /&gt;[ 0.000000] psci: Using standard PSCI v0.2 function IDs&lt;BR /&gt;[ 0.000000] psci: Trusted OS migration not required&lt;BR /&gt;[ 0.000000] psci: SMC Calling Convention v1.1&lt;BR /&gt;[ 0.000000] percpu: Embedded 20 pages/cpu s41176 r8192 d32552 u81920&lt;BR /&gt;[ 0.000000] Detected VIPT I-cache on CPU0&lt;BR /&gt;[ 0.000000] CPU features: detected: GIC system register CPU interface&lt;BR /&gt;[ 0.000000] CPU features: detected: ARM erratum 845719&lt;BR /&gt;[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 1540096&lt;BR /&gt;[ 0.000000] Policy zone: Normal&lt;BR /&gt;[ 0.000000] Kernel command line: console=ttymxc1,115200 root=/dev/mmcblk2p2 rootwait rw&lt;BR /&gt;[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)&lt;BR /&gt;[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)&lt;BR /&gt;[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off&lt;BR /&gt;[ 0.000000] software IO TLB: mapped [mem 0x00000000c0000000-0x00000000c4000000] (64MB)&lt;BR /&gt;[ 0.000000] Memory: 4760656K/6258688K available (18560K kernel code, 1534K rwdata, 7072K rodata, 2944K init, 541K bss, 514992K reserved, 983040K cma&lt;BR /&gt;-reserved)&lt;/P&gt;&lt;P&gt;So with 6Gb setting kernel and u-boot work correct :-). But not work with 8Gb. And i have a question.&lt;/P&gt;&lt;P&gt;Has anyone tried using 8Gb on imx8mp(supported by documentation)???&lt;/P&gt;&lt;P&gt;Why in the utility DDR Stress Tool you can choose only 6GB Max density???&lt;/P&gt;</description>
      <pubDate>Fri, 10 Mar 2023 13:38:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Add-DDR4-memory-to-imx8mp/m-p/1613167#M202571</guid>
      <dc:creator>VoVan</dc:creator>
      <dc:date>2023-03-10T13:38:36Z</dc:date>
    </item>
    <item>
      <title>回复： Add DDR4 memory to imx8mp</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Add-DDR4-memory-to-imx8mp/m-p/1613940#M202638</link>
      <description>&lt;P&gt;With this code:&lt;/P&gt;&lt;P&gt;mw 0x3d400200, 0x1f&lt;BR /&gt;&lt;STRONG&gt;mw&amp;nbsp;0x3d400204, 0x3f0909&lt;/STRONG&gt;&lt;BR /&gt;mw&amp;nbsp;0x3d400208, 0x700&lt;BR /&gt;mw&amp;nbsp;0x3d40020c, 0x0&lt;BR /&gt;mw&amp;nbsp;0x3d400210, 0x1f1f&lt;BR /&gt;mw 0x3d400214, 0x8080808&lt;BR /&gt;mw&amp;nbsp;0x3d400218, 0x8080808&lt;BR /&gt;mw&amp;nbsp;0x3d40021c, 0xf08&lt;BR /&gt;&lt;STRONG&gt;mw&amp;nbsp;0x3d400220, 0xa01&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;or with this:&lt;/P&gt;&lt;P&gt;mw 0x3d400200, 0x1f&lt;BR /&gt;&lt;STRONG&gt;mw&amp;nbsp;0x3d400204, 0x3f0a0a&lt;/STRONG&gt;&lt;BR /&gt;mw&amp;nbsp;0x3d400208, 0x700&lt;BR /&gt;mw&amp;nbsp;0x3d40020c, 0x0&lt;BR /&gt;mw&amp;nbsp;0x3d400210, 0x1f1f&lt;BR /&gt;mw 0x3d400214, 0x8080808&lt;BR /&gt;mw&amp;nbsp;0x3d400218, 0x8080808&lt;BR /&gt;mw&amp;nbsp;0x3d40021c, 0xf08&lt;BR /&gt;&lt;STRONG&gt;mw&amp;nbsp;0x3d400220, 0x801&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;I have the same results( work 6Gb DDR4, but don't work other 2Gb).&lt;/P&gt;&lt;P&gt;u-boot=&amp;gt; mtest 60000000 1c0000000&lt;BR /&gt;Testing 60000000 ... 1c0000000:&lt;BR /&gt;Pattern FFFFFFFFFFFFFFFF Writing... Reading...n: 28: 27&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 13 Mar 2023 09:55:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Add-DDR4-memory-to-imx8mp/m-p/1613940#M202638</guid>
      <dc:creator>VoVan</dc:creator>
      <dc:date>2023-03-13T09:55:51Z</dc:date>
    </item>
    <item>
      <title>回复： Add DDR4 memory to imx8mp</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Add-DDR4-memory-to-imx8mp/m-p/1613964#M202640</link>
      <description>&lt;P&gt;From imx8mp xls(c31 - total data bus width = 32 bit):&lt;/P&gt;&lt;P&gt;addrmap_bank_b0 = (if c31 == 32) ? 9 : 7 = 0x9;&lt;/P&gt;&lt;P&gt;From imx8mm mini xls(c31 - total data bus width = 32 bit, C28 - number of bank group = 2):&lt;/P&gt;&lt;P&gt;addrmap_bank_b0 = ((7 + C31/16) + (C28 - 1 ))) = 0xa&lt;/P&gt;&lt;P&gt;addrmap_bank_b0 = ((7 + C31/16) + (C28 - 1 ))) = 0x9, when C28 = 1&lt;/P&gt;&lt;P&gt;imx8mp xls don't use c28 setting, imx8mm use c28 .........&lt;/P&gt;</description>
      <pubDate>Mon, 13 Mar 2023 10:25:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Add-DDR4-memory-to-imx8mp/m-p/1613964#M202640</guid>
      <dc:creator>VoVan</dc:creator>
      <dc:date>2023-03-13T10:25:21Z</dc:date>
    </item>
    <item>
      <title>Re: Add DDR4 memory to imx8mp</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Add-DDR4-memory-to-imx8mp/m-p/1628168#M203756</link>
      <description>&lt;P&gt;I solved the problem. I got the whole range - 8Gb.&lt;BR /&gt;For this, I divided the memory into two regions: 3Gb and 5Gb, despite the fact that I have two DDR4 memory 4Gb each.&lt;BR /&gt;There is also a limit on the maximum size of memory in the optee-os package (6Gb) for imx8mp and other platforms.&lt;BR /&gt;I am attaching patches for imx8mp 5.4.70 yocto, maybe someone will need them.&lt;/P&gt;&lt;P&gt;Result of work:&lt;BR /&gt;u-boot=&amp;gt; mtest 60000000 240000000&lt;BR /&gt;Testing 60000000 ... 240000000:&lt;BR /&gt;Pattern 00000000 Writing... Reading...ading...Iteration: 65&lt;/P&gt;&lt;P&gt;DDR4 memory 8Gigabytes: 2 bank group adresses(K4ABG165WA).&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Wed, 05 Apr 2023 09:48:56 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Add-DDR4-memory-to-imx8mp/m-p/1628168#M203756</guid>
      <dc:creator>VoVan</dc:creator>
      <dc:date>2023-04-05T09:48:56Z</dc:date>
    </item>
    <item>
      <title>Re: Add DDR4 memory to imx8mp</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Add-DDR4-memory-to-imx8mp/m-p/1628171#M203757</link>
      <description>&lt;P&gt;Special thanks to nxp specialists for the hint on splitting memory regions into 3 and 5 Gb!!!&lt;/P&gt;</description>
      <pubDate>Wed, 05 Apr 2023 09:53:52 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Add-DDR4-memory-to-imx8mp/m-p/1628171#M203757</guid>
      <dc:creator>VoVan</dc:creator>
      <dc:date>2023-04-05T09:53:52Z</dc:date>
    </item>
    <item>
      <title>Re: Add DDR4 memory to imx8mp</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Add-DDR4-memory-to-imx8mp/m-p/1680326#M208523</link>
      <description>&lt;P&gt;hello,&lt;/P&gt;
&lt;P&gt;so could you share the last value of&amp;nbsp;&lt;SPAN&gt;BANK GROUP addresses&amp;nbsp;.1 or 2? many thanks.&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Mon, 03 Jul 2023 08:43:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Add-DDR4-memory-to-imx8mp/m-p/1680326#M208523</guid>
      <dc:creator>kenli</dc:creator>
      <dc:date>2023-07-03T08:43:17Z</dc:date>
    </item>
  </channel>
</rss>

