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    <title>i.MX ProcessorsのトピックIMX6SX SDB</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX6SX-SDB/m-p/1605888#M202036</link>
    <description>&lt;P&gt;Hi experts&amp;nbsp;&lt;/P&gt;&lt;P&gt;i am designing&amp;nbsp; a custom board based on imx6sx sdb&lt;/P&gt;&lt;P&gt;i want to a custom board&amp;nbsp; to boot from QSPI flash on QSPI1 but QSPI2 ( which is a case of imx6sx sdb)&lt;/P&gt;&lt;P&gt;i have some questions in moving QSPI2A flash (from SDB) to QSPIA&lt;/P&gt;&lt;P&gt;1.&amp;nbsp; on imx6sx sdb&amp;nbsp; &amp;nbsp;there is a "PMIC_INT_B" which connected between cpu and pmic&amp;nbsp;&lt;/P&gt;&lt;P&gt;but i can't find any source in u-boot and kernel,&amp;nbsp; there is no irq related source in pmic driver&lt;/P&gt;&lt;P&gt;what does&amp;nbsp; the PMIC_INT_B do&amp;nbsp; &amp;nbsp; ?&amp;nbsp; &amp;nbsp;if i missed something , let me know&amp;nbsp;&lt;/P&gt;&lt;P&gt;2. in u-boot&amp;nbsp; there is a qspi_header ,&amp;nbsp; do i need to modify that&amp;nbsp; file ?&amp;nbsp;&lt;/P&gt;&lt;P&gt;in qspi_header&amp;nbsp; &amp;nbsp;," the Serial Flash Port B selection " and "CS1 on Port A"&amp;nbsp; , i can't understand what they do&amp;nbsp;&lt;/P&gt;&lt;P&gt;in which situation should i use that configuration ?&lt;/P&gt;&lt;P&gt;3&amp;nbsp; in QSPI booting,&amp;nbsp; QSPIA/B , SS0,SS1 are all supported ?&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;thank you&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
    <pubDate>Mon, 27 Feb 2023 07:08:51 GMT</pubDate>
    <dc:creator>hyoungkikim</dc:creator>
    <dc:date>2023-02-27T07:08:51Z</dc:date>
    <item>
      <title>IMX6SX SDB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6SX-SDB/m-p/1605888#M202036</link>
      <description>&lt;P&gt;Hi experts&amp;nbsp;&lt;/P&gt;&lt;P&gt;i am designing&amp;nbsp; a custom board based on imx6sx sdb&lt;/P&gt;&lt;P&gt;i want to a custom board&amp;nbsp; to boot from QSPI flash on QSPI1 but QSPI2 ( which is a case of imx6sx sdb)&lt;/P&gt;&lt;P&gt;i have some questions in moving QSPI2A flash (from SDB) to QSPIA&lt;/P&gt;&lt;P&gt;1.&amp;nbsp; on imx6sx sdb&amp;nbsp; &amp;nbsp;there is a "PMIC_INT_B" which connected between cpu and pmic&amp;nbsp;&lt;/P&gt;&lt;P&gt;but i can't find any source in u-boot and kernel,&amp;nbsp; there is no irq related source in pmic driver&lt;/P&gt;&lt;P&gt;what does&amp;nbsp; the PMIC_INT_B do&amp;nbsp; &amp;nbsp; ?&amp;nbsp; &amp;nbsp;if i missed something , let me know&amp;nbsp;&lt;/P&gt;&lt;P&gt;2. in u-boot&amp;nbsp; there is a qspi_header ,&amp;nbsp; do i need to modify that&amp;nbsp; file ?&amp;nbsp;&lt;/P&gt;&lt;P&gt;in qspi_header&amp;nbsp; &amp;nbsp;," the Serial Flash Port B selection " and "CS1 on Port A"&amp;nbsp; , i can't understand what they do&amp;nbsp;&lt;/P&gt;&lt;P&gt;in which situation should i use that configuration ?&lt;/P&gt;&lt;P&gt;3&amp;nbsp; in QSPI booting,&amp;nbsp; QSPIA/B , SS0,SS1 are all supported ?&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;thank you&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 27 Feb 2023 07:08:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6SX-SDB/m-p/1605888#M202036</guid>
      <dc:creator>hyoungkikim</dc:creator>
      <dc:date>2023-02-27T07:08:51Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6SX SDB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6SX-SDB/m-p/1609195#M202303</link>
      <description>&lt;DIV&gt;&lt;SPAN&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/952"&gt;@hyoungkikim&lt;/a&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;I hope you are doing well&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;Please find the answer below.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;1)&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;PMIC_INT_B is an interrupt&amp;nbsp;signal, when this pin is low&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;interrupt&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;will be generated.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;Please refer to section&amp;nbsp;&lt;/SPAN&gt;6.5.3 Interrupt handling from the&amp;nbsp;&lt;A href="https://www.nxp.com/docs/en/data-sheet/MMPF0200.pdf" target="_blank" rel="noopener" data-saferedirecturl="https://www.google.com/url?q=https://www.nxp.com/docs/en/data-sheet/MMPF0200.pdf&amp;amp;source=gmail&amp;amp;ust=1677928052546000&amp;amp;usg=AOvVaw0tq2SsTF1MHOTUmpYRBt-_"&gt;datasheet&lt;/A&gt;.&lt;/DIV&gt;
&lt;DIV&gt;&lt;SPAN&gt;2) For the configuration of QSPI one can refer the section&amp;nbsp;&lt;/SPAN&gt;8.6.3 QuadSPI configuration parameters from the reference manual.&lt;/DIV&gt;
&lt;P&gt;&lt;SPAN&gt;3) Yes, For more details kindly refer to&amp;nbsp;&lt;/SPAN&gt;&lt;SPAN&gt;Table 8-27. QSPI IOMUX pin configuration in the Reference manual.&lt;/SPAN&gt;&lt;/P&gt;
&lt;DIV&gt;&lt;SPAN&gt;for more information, one can refer below thread.&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/iMX6SX-QSPI-boot/m-p/437517" target="_blank" rel="noopener" data-saferedirecturl="https://www.google.com/url?q=https://community.nxp.com/t5/i-MX-Processors/iMX6SX-QSPI-boot/m-p/437517&amp;amp;source=gmail&amp;amp;ust=1677928052546000&amp;amp;usg=AOvVaw1cXvIxeLWiEWgWmaC1J2Qs"&gt;&amp;nbsp;iMX6SX QSPI boot&lt;/A&gt;&lt;SPAN&gt;&lt;BR /&gt;&lt;/SPAN&gt;&lt;/DIV&gt;
&lt;DIV&gt;&lt;A href="https://community.nxp.com/t5/i-MX-Processors/Booting-U-boot-on-i-MX6-Solo-X-from-QSPI-on-SABRE-SD/m-p/414909" target="_blank" rel="noopener" data-saferedirecturl="https://www.google.com/url?q=https://community.nxp.com/t5/i-MX-Processors/Booting-U-boot-on-i-MX6-Solo-X-from-QSPI-on-SABRE-SD/m-p/414909&amp;amp;source=gmail&amp;amp;ust=1677928052546000&amp;amp;usg=AOvVaw0yQrWyDuWb9CUMWkqxb5bg"&gt;Booting U-boot on i.MX6 Solo X from QSPI on SABRE-SD&lt;/A&gt;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Thanks &amp;amp; Regards&lt;/DIV&gt;
&lt;DIV&gt;Sanket Parekh&lt;/DIV&gt;</description>
      <pubDate>Fri, 03 Mar 2023 12:22:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6SX-SDB/m-p/1609195#M202303</guid>
      <dc:creator>Sanket_Parekh</dc:creator>
      <dc:date>2023-03-03T12:22:30Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6SX SDB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6SX-SDB/m-p/1609929#M202365</link>
      <description>&lt;P&gt;Hi&amp;nbsp; Sanket_Parekh&lt;/P&gt;&lt;P&gt;your reply about QSPI will be of great help&lt;/P&gt;&lt;P&gt;about&amp;nbsp; PMIC_INT_B&amp;nbsp; &amp;nbsp; does u-boot and kernel from LF_v5.15.52-2.1.0&amp;nbsp; &amp;nbsp;use that PIN ?&amp;nbsp;&lt;/P&gt;&lt;P&gt;i couldn't find any source about it&amp;nbsp; ,&amp;nbsp; i want to use&amp;nbsp; QSPI1 as boot device , so i tried to find&amp;nbsp; QSPI1 Pin related&amp;nbsp; source and remove or commnet out , i almost found them except&amp;nbsp; PMIC_INT_B&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;thank you&amp;nbsp;&lt;/P&gt;&lt;P&gt;sincerely&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;</description>
      <pubDate>Mon, 06 Mar 2023 09:56:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6SX-SDB/m-p/1609929#M202365</guid>
      <dc:creator>hyoungkikim</dc:creator>
      <dc:date>2023-03-06T09:56:44Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6SX SDB</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6SX-SDB/m-p/1614656#M202694</link>
      <description>&lt;DIV&gt;Hi &lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/952"&gt;@hyoungkikim&lt;/a&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;I hope you are doing well&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Yes, there is no such reference in the uboot or kernel as the PMIC_INT_B pin is related to the PMIC. We don't think so there is anything to do with this pin for the QSPI boot.&lt;/DIV&gt;
&lt;DIV&gt;&amp;nbsp;&lt;/DIV&gt;
&lt;DIV&gt;Thanks &amp;amp; Regards&lt;/DIV&gt;
&lt;DIV&gt;Sanket Parekh&lt;/DIV&gt;
&lt;P&gt;&lt;LI-WRAPPER&gt;&lt;/LI-WRAPPER&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 14 Mar 2023 07:27:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6SX-SDB/m-p/1614656#M202694</guid>
      <dc:creator>Sanket_Parekh</dc:creator>
      <dc:date>2023-03-14T07:27:26Z</dc:date>
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