i.MX ProcessorsのトピックError response from the Bus while trying to decode video

Error response from the Bus while trying to decode video

PiotrKrygier — Wed, 15 Feb 2023 09:42:49 GMT

Hello,

I'm creating kernel driver for my client purposes, integrating VPU G1 capabilities of IMX8M Mini. No matter what I try, when I write 0x1 to SWREG1, starting decoding, I get "0x2101" from this register, which translates to:

- Decoder enabled

- Decoder IRQ

- Interrupt status bit bus. Error response from bus.

First two are OK, but the third one is a blocker. I passed DMA address received from

vb2_dma_contig_plane_dma_addr()

function to both SWREG12 and SWREG13. This memory should be HW accessible physical memory. If I am not mistaken, bus error means that there is a problem with memory access, alignment or something other related to memory. What other registers do I HAVE TO set up for this work? I have already checked VPU_BLK_CTRL register, G1 has all fuses enabled and is operating. All I want to get is another error like "SW_DEC_ERROR_INT" or "SW_DEC_BUFFER_INT".

Best regards,

Piotr

Re: Error response from the Bus while trying to decode video

Bio_TICFSL — Tue, 21 Feb 2023 14:32:28 GMT

Hello,

The maximum size of the encoded frame depends on the input picture. If the encoder reaches the end of the output buffer, it will discard the current frame and return
VCENC_OUTPUT_BUFFER_OVERFLOW. Even if the current frame is lost, the encoding process can continue with a new frame which will be INTRA coded to assure that any errors are not propagated. You have to alignment in order to pass this buffer.

Regards

Re: Error response from the Bus while trying to decode video

PiotrKrygier — Tue, 21 Feb 2023 16:06:37 GMT

Hello,

I'm sorry, but I have trouble understanding. I am working on a decoder, using direct access to VPU registers, not VPU API, so I can't get an error like VCENC_OUTPUT_BUFFER_OVERFLOW. All I'm getting is bus error in SWREG1 register.