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    <title>topic mipi csi 2 in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/mipi-csi-2/m-p/1594157#M201104</link>
    <description>&lt;P&gt;csi1_bridge: csi1_bridge@30b80000 {&lt;BR /&gt;compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi";&lt;BR /&gt;reg = &amp;lt;0x0 0x30b80000 0x0 0x10000&amp;gt;;&lt;BR /&gt;interrupts = &amp;lt;GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH&amp;gt;;&lt;BR /&gt;clocks = &amp;lt;&amp;amp;clk IMX8MQ_CLK_DUMMY&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI1_ROOT&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_DUMMY&amp;gt;;&lt;BR /&gt;clock-names = "disp-axi", "csi_mclk", "disp_dcic";&lt;BR /&gt;dma-coherent;&lt;BR /&gt;status = "disabled";&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;csi2_bridge: csi2_bridge@30a90000 {&lt;BR /&gt;compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi";&lt;BR /&gt;reg = &amp;lt;0x0 0x30a90000 0x0 0x10000&amp;gt;;&lt;BR /&gt;interrupts = &amp;lt;GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH&amp;gt;;&lt;BR /&gt;clocks = &amp;lt;&amp;amp;clk IMX8MQ_CLK_DUMMY&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI2_ROOT&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_DUMMY&amp;gt;;&lt;BR /&gt;clock-names = "disp-axi", "csi_mclk", "disp_dcic";&lt;BR /&gt;dma-coherent;&lt;BR /&gt;status = "disabled";&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;mipi_csi_1: mipi_csi1@30b60000 {&lt;BR /&gt;compatible = "fsl,mxc-mipi-csi2_yav";&lt;BR /&gt;reg = &amp;lt;0x0 0x30b60000 0x0 0x1000&amp;gt;; /* MIPI CSI1 Controller base addr */&lt;BR /&gt;interrupts = &amp;lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&amp;gt;;&lt;BR /&gt;clocks = &amp;lt;&amp;amp;clk IMX8MQ_CLK_DUMMY&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI1_CORE&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI1_ESC&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI1_PHY_REF&amp;gt;;&lt;BR /&gt;clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";&lt;BR /&gt;assigned-clocks = &amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI1_CORE&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI1_PHY_REF&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI1_ESC&amp;gt;;&lt;BR /&gt;assigned-clock-rates = &amp;lt;266000000&amp;gt;, &amp;lt;333000000&amp;gt;, &amp;lt;66000000&amp;gt;;&lt;BR /&gt;power-domains = &amp;lt;&amp;amp;mipi_csi1_pd&amp;gt;;&lt;BR /&gt;csis-phy-reset = &amp;lt;&amp;amp;src 0x4c 7&amp;gt;;&lt;BR /&gt;phy-gpr = &amp;lt;&amp;amp;gpr 0x88&amp;gt;;&lt;BR /&gt;status = "disabled";&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;mipi_csi_2: mipi_csi2@30a70000 {&lt;BR /&gt;compatible = "fsl,mxc-mipi-csi2_yav";&lt;BR /&gt;reg = &amp;lt;0x0 0x30a70000 0x0 0x1000&amp;gt;; /* MIPI CSI2 Controller base addr */&lt;BR /&gt;interrupts = &amp;lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&amp;gt;;&lt;BR /&gt;clocks = &amp;lt;&amp;amp;clk IMX8MQ_CLK_DUMMY&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI2_CORE&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI2_ESC&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI2_PHY_REF&amp;gt;;&lt;BR /&gt;clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";&lt;BR /&gt;assigned-clocks = &amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI2_CORE&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI2_PHY_REF&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI2_ESC&amp;gt;;&lt;BR /&gt;assigned-clock-rates = &amp;lt;266000000&amp;gt;, &amp;lt;333000000&amp;gt;, &amp;lt;66000000&amp;gt;;&lt;BR /&gt;power-domains = &amp;lt;&amp;amp;mipi_csi2_pd&amp;gt;;&lt;BR /&gt;csis-phy-reset = &amp;lt;&amp;amp;src 0x50 7&amp;gt;;&lt;BR /&gt;phy-gpr = &amp;lt;&amp;amp;gpr 0xa4&amp;gt;;&lt;BR /&gt;status = "disabled";&lt;BR /&gt;};&lt;BR /&gt;I am trying to read the mipi data off a camera I have attached to a coral SOM. I can read all of the registers on the camera but I cannot read the frame data. The camera is connected to mipi csi 2. I am wondering what I am doing wrong. I have swapped the mipi_csi_1 and 2 registers and that also does not seem to work. Any help on how to read the frame data would be much appreciated. Thank you&lt;/P&gt;</description>
    <pubDate>Mon, 06 Feb 2023 18:58:57 GMT</pubDate>
    <dc:creator>e34605</dc:creator>
    <dc:date>2023-02-06T18:58:57Z</dc:date>
    <item>
      <title>mipi csi 2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/mipi-csi-2/m-p/1594157#M201104</link>
      <description>&lt;P&gt;csi1_bridge: csi1_bridge@30b80000 {&lt;BR /&gt;compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi";&lt;BR /&gt;reg = &amp;lt;0x0 0x30b80000 0x0 0x10000&amp;gt;;&lt;BR /&gt;interrupts = &amp;lt;GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH&amp;gt;;&lt;BR /&gt;clocks = &amp;lt;&amp;amp;clk IMX8MQ_CLK_DUMMY&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI1_ROOT&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_DUMMY&amp;gt;;&lt;BR /&gt;clock-names = "disp-axi", "csi_mclk", "disp_dcic";&lt;BR /&gt;dma-coherent;&lt;BR /&gt;status = "disabled";&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;csi2_bridge: csi2_bridge@30a90000 {&lt;BR /&gt;compatible = "fsl,imx8mq-csi", "fsl,imx6s-csi";&lt;BR /&gt;reg = &amp;lt;0x0 0x30a90000 0x0 0x10000&amp;gt;;&lt;BR /&gt;interrupts = &amp;lt;GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH&amp;gt;;&lt;BR /&gt;clocks = &amp;lt;&amp;amp;clk IMX8MQ_CLK_DUMMY&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI2_ROOT&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_DUMMY&amp;gt;;&lt;BR /&gt;clock-names = "disp-axi", "csi_mclk", "disp_dcic";&lt;BR /&gt;dma-coherent;&lt;BR /&gt;status = "disabled";&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;mipi_csi_1: mipi_csi1@30b60000 {&lt;BR /&gt;compatible = "fsl,mxc-mipi-csi2_yav";&lt;BR /&gt;reg = &amp;lt;0x0 0x30b60000 0x0 0x1000&amp;gt;; /* MIPI CSI1 Controller base addr */&lt;BR /&gt;interrupts = &amp;lt;GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH&amp;gt;;&lt;BR /&gt;clocks = &amp;lt;&amp;amp;clk IMX8MQ_CLK_DUMMY&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI1_CORE&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI1_ESC&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI1_PHY_REF&amp;gt;;&lt;BR /&gt;clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";&lt;BR /&gt;assigned-clocks = &amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI1_CORE&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI1_PHY_REF&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI1_ESC&amp;gt;;&lt;BR /&gt;assigned-clock-rates = &amp;lt;266000000&amp;gt;, &amp;lt;333000000&amp;gt;, &amp;lt;66000000&amp;gt;;&lt;BR /&gt;power-domains = &amp;lt;&amp;amp;mipi_csi1_pd&amp;gt;;&lt;BR /&gt;csis-phy-reset = &amp;lt;&amp;amp;src 0x4c 7&amp;gt;;&lt;BR /&gt;phy-gpr = &amp;lt;&amp;amp;gpr 0x88&amp;gt;;&lt;BR /&gt;status = "disabled";&lt;BR /&gt;};&lt;/P&gt;&lt;P&gt;mipi_csi_2: mipi_csi2@30a70000 {&lt;BR /&gt;compatible = "fsl,mxc-mipi-csi2_yav";&lt;BR /&gt;reg = &amp;lt;0x0 0x30a70000 0x0 0x1000&amp;gt;; /* MIPI CSI2 Controller base addr */&lt;BR /&gt;interrupts = &amp;lt;GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH&amp;gt;;&lt;BR /&gt;clocks = &amp;lt;&amp;amp;clk IMX8MQ_CLK_DUMMY&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI2_CORE&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI2_ESC&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI2_PHY_REF&amp;gt;;&lt;BR /&gt;clock-names = "clk_apb", "clk_core", "clk_esc", "clk_pxl";&lt;BR /&gt;assigned-clocks = &amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI2_CORE&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI2_PHY_REF&amp;gt;,&lt;BR /&gt;&amp;lt;&amp;amp;clk IMX8MQ_CLK_CSI2_ESC&amp;gt;;&lt;BR /&gt;assigned-clock-rates = &amp;lt;266000000&amp;gt;, &amp;lt;333000000&amp;gt;, &amp;lt;66000000&amp;gt;;&lt;BR /&gt;power-domains = &amp;lt;&amp;amp;mipi_csi2_pd&amp;gt;;&lt;BR /&gt;csis-phy-reset = &amp;lt;&amp;amp;src 0x50 7&amp;gt;;&lt;BR /&gt;phy-gpr = &amp;lt;&amp;amp;gpr 0xa4&amp;gt;;&lt;BR /&gt;status = "disabled";&lt;BR /&gt;};&lt;BR /&gt;I am trying to read the mipi data off a camera I have attached to a coral SOM. I can read all of the registers on the camera but I cannot read the frame data. The camera is connected to mipi csi 2. I am wondering what I am doing wrong. I have swapped the mipi_csi_1 and 2 registers and that also does not seem to work. Any help on how to read the frame data would be much appreciated. Thank you&lt;/P&gt;</description>
      <pubDate>Mon, 06 Feb 2023 18:58:57 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/mipi-csi-2/m-p/1594157#M201104</guid>
      <dc:creator>e34605</dc:creator>
      <dc:date>2023-02-06T18:58:57Z</dc:date>
    </item>
    <item>
      <title>Re: mipi csi 2</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/mipi-csi-2/m-p/1594419#M201125</link>
      <description>&lt;P&gt;your information is too limited,did you use nxp board or your customized board? if you use your own board,&amp;nbsp; firstly could you confirm if your HW connection is correct or not? do you get any correct clock? if yes, pls send your logfile with me&lt;/P&gt;</description>
      <pubDate>Tue, 07 Feb 2023 06:33:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/mipi-csi-2/m-p/1594419#M201125</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2023-02-07T06:33:06Z</dc:date>
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